hcintmsk2

This register reflects the mask for each channel status described in the previous section.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB0054C
usb1 0xFFB40000 0xFFB4054C

Offset: 0x54C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

frm_lst_rollintrmsk

RW 0x0

Reserved

bnaintrmsk

RW 0x0

Reserved

ahberrmsk

RW 0x0

chhltdmsk

RW 0x0

xfercomplmsk

RW 0x0

hcintmsk2 Fields

Bit Name Description Access Reset
13 frm_lst_rollintrmsk

This bit is valid only when Scatter/Gather DMA mode is enabled.

Value Description
0x0 Mask
0x1 No mask
RW 0x0
11 bnaintrmsk

This bit is valid only when Scatter/Gather DMA mode is enabled.

Value Description
0x0 Mask
0x1 No mask
RW 0x0
2 ahberrmsk

In scatter/gather DMA mode for host, interrupts will not be generated due to the corresponding bits set in HCINTn.

Value Description
0x0 Mask
0x1 No mask
RW 0x0
1 chhltdmsk

Channel Halted.

Value Description
0x0 Mask
0x1 No mask
RW 0x0
0 xfercomplmsk

Transfer complete.

Value Description
0x0 Mask
0x1 No mask
RW 0x0