GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 849710
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application 5. Designing with the IP Core 6. Designing the IP Solution 7. Sharing Clocking and Applying SDC Constraints 8. Runtime Flow 9. Simulating the IP 10. Validating the IP 11. Appendix A: Functional Description 12. Registers 13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
1. Overview x
1.1. About the GTS Dynamic Reconfiguration Controller IP 1.2. About the Document 1.3. Key Concepts 1.4. System Level Block Diagram 1.5. Design Checklist 1.6. IP Design Flow 1.7. Dynamic Reconfiguration 1.8. Design Considerations 1.9. Design Migration Guidelines 1.10. Design Flow Requirements
1.1. About the GTS Dynamic Reconfiguration Controller IP x
1.1.1. Release Information 1.1.2. Features 1.1.3. High-Level Functional Overview 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training 1.2.6. GTS Dynamic Reconfiguration Target Applications
2. Quick Start Guide x
2.1. Steps to Generate and Run the Design Example 2.2. Steps to Create a Custom Dynamic Reconfiguration Design
2.1. Steps to Generate and Run the Design Example x
2.1.1. Generating the Design Example 2.1.2. Compiling the Design Example 2.1.3. Simulating the Design Example 2.1.4. Validating the Design Example
2.2. Steps to Create a Custom Dynamic Reconfiguration Design x
2.2.1. Simulating the Custom Design 2.2.2. Validating the Custom Design
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles 3.3. Generating HDL for Synthesis and Simulation 3.4. Using the Dynamic Reconfiguration Assignment Editor 3.5. Generating HSSI Dynamic Reconfiguration IP 3.6. Generating the Design Example 3.7. Compiling the Design Example
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles x
3.2.1. Configuring the IP
3.2.1. Configuring the IP x
3.2.1.1. Configuring the IP Presets 3.2.1.2. Configuring the IP Parameters
3.4. Using the Dynamic Reconfiguration Assignment Editor x
3.4.1. Quartus User Flow
3.4.1. Quartus User Flow x
3.4.1.1. IP List 3.4.1.2. Dynamic Reconfiguration Group List 3.4.1.3. Properties 3.4.1.4. DR Group Visualization Pane 3.4.1.5. Messages Pane
3.6. Generating the Design Example x
3.6.1. Generated Directory Structure and Files
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Implementing Required AVMM Interface 4.6. Control and Status Interface 4.7. Implementing Mux Selector Interface 4.8. Implementing SRC Interface 4.9. Implementing Local AVMM Interface 4.10. Connecting the Interfaces 4.11. Signal Functions 4.12. Integrating the IP With User Logic 4.13. Integrating the IP With Your Board 4.14. Integrating the IP on the Stack With a Software Driver
5. Designing with the IP Core x
5.1. Release Constraints 5.2. DR Design Guidelines
6. Designing the IP Solution x
6.1. Dynamic Reconfiguration QSF Settings 6.2. Defining DR Combinations 6.3. Instantiating the Generated DR Group 6.4. Generating and Instantiating the DR Controller
9. Simulating the IP x
9.1. Design Example Features 9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench 9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench
9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench x
9.2.1. Simulating the Design Example
9.2.1. Simulating the Design Example x
9.2.1.1. Simulating the Testbench Flow 9.2.1.2. Verifying the Simulation Results
9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench x
9.3.1. Simulating the Design Example
9.3.1. Simulating the Design Example x
9.3.1.1. Verifying the Simulation Results
10. Validating the IP x
10.1. List of Switches on the Developer Kit 10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate 10.3. Testing the Hardware Design Example for Ethernet to CPRI 10.4. Troubleshooting and Debugging Issues
10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate x
10.2.1. Configure the Clocks in Hardware 10.2.2. Program the FPGA 10.2.3. Running the Hardware Test
10.3. Testing the Hardware Design Example for Ethernet to CPRI x
10.3.1. Running the Hardware Test
11. Appendix A: Functional Description x
11.1. AVMM Clock Crossing Bridge 11.2. AVMM Decoder 11.3. Mux Sel, Local AVMM, and SRC Interface 11.4. Dynamic Reconfiguration CSR
12. Registers x
12.1. Configuration Registers 12.2. GTS Transceiver PHY Design Example: Registers 12.3. Ethernet to CPRI Design Example: Registers
12.1. Configuration Registers x
12.1.1. Register Next ID Configuration 0 12.1.2. Register Next ID Configuration 1 12.1.3. Register Next ID Configuration 2 12.1.4. Register Next ID Configuration 3 12.1.5. Register Next ID Configuration 4 12.1.6. Register Next ID Configuration 5 12.1.7. Register Next ID Configuration 6 12.1.8. Register Next ID Configuration 7 12.1.9. Register Next ID Configuration 8 12.1.10. Register Next ID Configuration 9 12.1.11. Register Next ID Configuration 10 12.1.12. Register Next ID Configuration 11 12.1.13. Register Next ID Configuration 12 12.1.14. Register Next ID Configuration 13 12.1.15. Register Next ID Configuration 14 12.1.16. Register Next ID Configuration 15 12.1.17. Register Next ID Configuration 16 12.1.18. Register Next ID Configuration 17 12.1.19. Register Next ID Configuration 18 12.1.20. Register Next ID Configuration 19 12.1.21. Register Trigger 12.1.22. Register Trigger Status 12.1.23. Register Error Configuration 12.1.24. Register Error Status
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide

9.3.1.1. Verifying the Simulation Results

The following sample output illustrates a successful simulation test run. 
m_a[0].lavmm_a_proc.rws_a: at time 15000000 fs
LAVMM activity on port 0 while disabled.
Info: "basic_avl_tb_top.sv", 155: basic_avl_tb_top.tc: at time 55000000 fs
Wait for DR Controller to be ready

DR_STATUS_L0: DR NIOSV is alive with DR Firmware (Buildtime: 2024-09-06 07:30:09)
DR_STATUS_L1: dr_startup_initialization()
DR_STATUS_L1: dr_mif_checksum():
DR_STATUS_L1: dr_mif_checksum() done (cksum = 0x8096)
DR_STATUS_L1: dr_load_profile(): next_id=0x1, next_id_act=1 (1=Active 0=Neutral), init_startup=1
DR_STATUS_L2: dr_onehot_mux_select_set(): profile_id=1, enable=1
DR_STATUS_L1: dr_load_profile() done (error = 0)
DR_STATUS_L1: dr_startup_initialization() done
DR_STATUS_L0: DR NIOS is ready
DR_STATUS_L0: DR NIOS waiting for trigger
Info: "basic_avl_tb_top.sv", 158: basic_avl_tb_top.tc: at time 5375000000 fs
Check CSR status
Info: "basic_avl_tb_top.sv", 167: basic_avl_tb_top.tc: at time 5610001000 fs
DR Controller state:5
Info: "basic_avl_tb_top.sv", 168: basic_avl_tb_top.tc: at time 5610001000 fs
Waiting for reset ack
Info: "basic_avl_tb_top.sv", 170: basic_avl_tb_top.tc: at time 13105000000 fs
Reset ack asserted
Info: "basic_avl_tb_top.sv", 172: basic_avl_tb_top.tc: at time 13155000000 fs
Reset deasserted

basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
basic_avl_tb_top.dut.dr_top_inst.tennm_ipfluxtop_global_mem_wrap_0.sf_rtl_ncrypt_inst.PROTECTED.Test_wpulse -          15797000000 (MSG_INFO) wpulse has been set to 010
rck0_per = 6400.000000
fast_per = 6399.360000
slow_per = 6400.640000
rck0_per = 6400.000000
rck0_per = 6400.000000
fast_per = 6399.360000
slow_per = 6400.640000
rck0_per = 6400.000000

Info: "basic_avl_tb_top.sv", 174: basic_avl_tb_top.tc: at time 33135000000 fs
ETH Tx ready
Info: "basic_avl_tb_top.sv", 176: basic_avl_tb_top.tc: at time 38165000000 fs
ETH Rx ready
Info: "basic_avl_tb_top.sv", 180: basic_avl_tb_top.tc: at time 48165000000 fs
Checking ethernet data
Info: "basic_avl_tb_top.sv", 186: basic_avl_tb_top.tc: at time 78165000000 fs
Ethernet Recieved All Expected Data Packets Correctly
Info: "basic_avl_tb_top.sv", 188: basic_avl_tb_top.tc: at time 78165000000 fs
Starting DR sequence from ETH to CPRI
Info: "basic_avl_tb_top.sv", 190: basic_avl_tb_top.tc: at time 78165000000 fs
Reset ETH
Info: "basic_avl_tb_top.sv", 194: basic_avl_tb_top.tc: at time 78165000000 fs
Reset CPRI
Info: "basic_avl_tb_top.sv", 198: basic_avl_tb_top.tc: at time 79165000000 fs
Waiting for reset ack
Info: "basic_avl_tb_top.sv", 200: basic_avl_tb_top.tc: at time 79165000000 fs
Reset ack asserted
Info: "basic_avl_tb_top.sv", 201: basic_avl_tb_top.tc: at time 79165000000 fs
Write from and to profile
Info: "basic_avl_tb_top.sv", 204: basic_avl_tb_top.tc: at time 79195001000 fs
Trigger DR
Info: "basic_avl_tb_top.sv", 206: basic_avl_tb_top.tc: at time 79235001000 fs
Wait for DR Ack....
DR_STATUS_L0: DR NIOS reconfiguration started 
DR_STATUS_L1: dr_load_sequence():

Info: "basic_avl_tb_top.sv", 198: basic_avl_tb_top.tc: at time 79165000000 fs
Waiting for reset ack
Info: "basic_avl_tb_top.sv", 200: basic_avl_tb_top.tc: at time 79165000000 fs
Reset ack asserted
Info: "basic_avl_tb_top.sv", 201: basic_avl_tb_top.tc: at time 79165000000 fs
Write from and to profile
Info: "basic_avl_tb_top.sv", 204: basic_avl_tb_top.tc: at time 79195001000 fs
Trigger DR
Info: "basic_avl_tb_top.sv", 206: basic_avl_tb_top.tc: at time 79235001000 fs
Wait for DR Ack....
DR_STATUS_L0: DR NIOS reconfiguration started 
DR_STATUS_L1: dr_load_sequence():

Info: "basic_avl_tb_top.sv", 208: basic_avl_tb_top.tc: at time 79605000000 fs
Wait for DR Config to be done....
DR_STATUS_L1: dr_load_profile(): next_id=0x1, next_id_act=0 (1=Active 0=Neutral), init_startup=0
DR_STATUS_L2: dr_src_get_pause_grant(): ch_mask 0x1
DR_STATUS_L2: dr_src_get_pause_grant() done
DR_STATUS_L2: dr_onehot_mux_select_set(): profile_id=1, enable=0
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0x25, num_ip_settings=4
DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0xdd, num_ip_settings=57
DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L1: dr_load_profile() done (error = 0)
DR_STATUS_L1: dr_load_profile(): next_id=0x2, next_id_act=1 (1=Active 0=Neutral), init_startup=0
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0x17b, num_ip_settings=42
DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L1: dr_load_ip_settings(): ch=0, ip_settings_ndx=0x227, num_ip_settings=47
DR_STATUS_L1: dr_load_ip_settings() done
DR_STATUS_L2: dr_onehot_mux_select_set(): profile_id=0, enable=1
DR_STATUS_L1: dr_load_profile() done (error = 0)
DR_STATUS_L2: dr_src_release_pause_request(): 0x1
DR_STATUS_L2: dr_src_release_pause_request() done
DR_STATUS_L1: dr_load_sequence() done, iteration to final profile successfully finish (iter=3)
DR_STATUS_L0: DR NIOS reconfiguration done
DR_STATUS_L0: DR NIOS ready for next trigger
DR_STATUS_L0: DR NIOS waiting for trigger

Info: "basic_avl_tb_top.sv", 211: basic_avl_tb_top.tc: at time 850505000000 fs
Check error status
Info: "basic_avl_tb_top.sv", 220: basic_avl_tb_top.tc: at time 850740001000 fs
DR Controller state:          5
Info: "basic_avl_tb_top.sv", 222: basic_avl_tb_top.tc: at time 850740001000 fs
Reset Deasserted
rck0_per = 6510.000000
fast_per = 6509.349000
slow_per = 6510.651000
rck0_per = 6510.000000
rck0_per = 6510.000000
fast_per = 6509.349000
slow_per = 6510.651000
rck0_per = 6510.000000

Info: "basic_avl_tb_top.sv", 227: basic_avl_tb_top.tc: at time 871760850000 fs
CPRI Tx ready
Info: "basic_avl_tb_top.sv", 229: basic_avl_tb_top.tc: at time 876094350000 fs
CPRI Rx ready
Waiting for 8b10b pattern aligned
*** waiting for hyperframe sync to assert...
Checking patteren status
** Channels have received data correctly!
Info: "basic_avl_tb_top.sv", 242: basic_avl_tb_top.tc: at time 948903323345 fs
Test case passed
$finish called from file "basic_avl_tb_top.sv", line 243.
$finish at simulation time         948903323345
           V C S   S i m u l a t i o n   R e p o r t 
Time: 948903323345 fs
CPU Time:   1028.890 seconds;       Data structure size:  25.5Mb
Fri May 16 15:29:53 2025
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