GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 849710
Date 10/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application 5. Designing with the IP Core 6. Designing the IP Solution 7. Sharing Clocking and Applying SDC Constraints 8. Runtime Flow 9. Simulating the IP 10. Validating the IP 11. Appendix A: Functional Description 12. Registers 13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
1. Overview x
1.1. About the GTS Dynamic Reconfiguration Controller IP 1.2. About the Document 1.3. Key Concepts 1.4. System Level Block Diagram 1.5. IP Design Flow 1.6. Dynamic Reconfiguration 1.7. Design Considerations
1.1. About the GTS Dynamic Reconfiguration Controller IP x
1.1.1. Release Information 1.1.2. Features 1.1.3. High-Level Functional Overview 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training 1.2.6. GTS Dynamic Reconfiguration Target Applications
2. Quick Start Guide x
2.1. Steps to Generate and Run the Design Example 2.2. Steps to Create a Custom Dynamic Reconfiguration Design
2.1. Steps to Generate and Run the Design Example x
2.1.1. Generating the Design Example 2.1.2. Compiling the Design Example 2.1.3. Simulating the Design Example 2.1.4. Validating the Design Example
2.2. Steps to Create a Custom Dynamic Reconfiguration Design x
2.2.1. Simulating the Custom Design 2.2.2. Validating the Custom Design
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles 3.3. Generating HDL for Synthesis and Simulation 3.4. Using the HSSI Support Logic Assignment Editor 3.5. HSSI Support Logic Generation 3.6. Generating the Design Example 3.7. Compiling the Design Example
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles x
3.2.1. Configuring the IP
3.2.1. Configuring the IP x
3.2.1.1. Configuring the IP Parameters
3.4. Using the HSSI Support Logic Assignment Editor x
3.4.1. Quartus User Flow
3.4.1. Quartus User Flow x
3.4.1.1. IP List 3.4.1.2. Dynamic Reconfiguration Group List 3.4.1.3. Properties 3.4.1.4. DR Group Visualization Pane 3.4.1.5. Messages Pane
3.6. Generating the Design Example x
3.6.1. Generated Directory Structure and Files
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application x
4.1. Implementing Required Clocking 4.2. Implementing Required Resets 4.3. Implementing Required AVMM Interface 4.4. Control and Status Interface 4.5. Implementing Mux Selector Interface 4.6. Implementing SRC Interface 4.7. Implementing Local AVMM Interface
5. Designing with the IP Core x
5.1. Release Constraints 5.2. DR Design Guidelines
6. Designing the IP Solution x
6.1. Dynamic Reconfiguration QSF Settings 6.2. Defining DR Combinations 6.3. Instantiating the Generated DR Group 6.4. Generating and Instantiating the DR Controller
9. Simulating the IP x
9.1. Design Example Features 9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench 9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench 9.4. Simulating the GTS PTP/CPRI Multirate FPGA IP Design Example Testbench 9.5. Simulating the GTS Triple-Speed Ethernet (TSE)/Multirate Ethernet IP Design Example Testbench
9.1. Design Example Features x
9.1.1. Simulating the Testbench Flow
9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench x
9.2.1. Simulating the Design Example
9.2.1. Simulating the Design Example x
9.2.1.1. Verifying the Simulation Results
9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench x
9.3.1. Simulating the Design Example
9.3.1. Simulating the Design Example x
9.3.1.1. Verifying the Simulation Results
9.4. Simulating the GTS PTP/CPRI Multirate FPGA IP Design Example Testbench x
9.4.1. Simulating the Design Example
9.4.1. Simulating the Design Example x
9.4.1.1. Verifying the Simulation Results
9.5. Simulating the GTS Triple-Speed Ethernet (TSE)/Multirate Ethernet IP Design Example Testbench x
9.5.1. Simulating the Design Example
9.5.1. Simulating the Design Example x
9.5.1.1. Verifying the Simulation Results
10. Validating the IP x
10.1. Testing the Hardware Design Example for PMA Direct PHY Multirate 10.2. Testing the Hardware Design Example for Ethernet to CPRI 10.3. Testing the Hardware Design Example for PTP/CPRI Multirate 10.4. Testing the Hardware Design Example for TSE/Multirate Ethernet 10.5. Troubleshooting and Debugging Issues
10.1. Testing the Hardware Design Example for PMA Direct PHY Multirate x
10.1.1. Configure the Clocks in Hardware 10.1.2. Program the FPGA 10.1.3. Running the Hardware Test
10.2. Testing the Hardware Design Example for Ethernet to CPRI x
10.2.1. Running the Hardware Test
10.3. Testing the Hardware Design Example for PTP/CPRI Multirate x
10.3.1. Running the Hardware Test
10.4. Testing the Hardware Design Example for TSE/Multirate Ethernet x
10.4.1. Running the Hardware Test
11. Appendix A: Functional Description x
11.1. AVMM Clock Crossing Bridge 11.2. AVMM Decoder 11.3. Mux Sel, Local AVMM, and SRC Interface 11.4. Dynamic Reconfiguration CSR
12. Registers x
12.1. Configuration Registers 12.2. GTS Transceiver PHY Design Example: Registers 12.3. Ethernet to CPRI Design Example: Registers 12.4. PTP/CPRI Multirate Design Example: Registers 12.5. TSE/Multirate Ethernet Design Example: Registers
12.1. Configuration Registers x
12.1.1. Register Next ID Configuration 0 12.1.2. Register Next ID Configuration 1 12.1.3. Register Next ID Configuration 2 12.1.4. Register Next ID Configuration 3 12.1.5. Register Next ID Configuration 4 12.1.6. Register Next ID Configuration 5 12.1.7. Register Next ID Configuration 6 12.1.8. Register Next ID Configuration 7 12.1.9. Register Next ID Configuration 8 12.1.10. Register Next ID Configuration 9 12.1.11. Register Next ID Configuration 10 12.1.12. Register Next ID Configuration 11 12.1.13. Register Next ID Configuration 12 12.1.14. Register Next ID Configuration 13 12.1.15. Register Next ID Configuration 14 12.1.16. Register Next ID Configuration 15 12.1.17. Register Next ID Configuration 16 12.1.18. Register Next ID Configuration 17 12.1.19. Register Next ID Configuration 18 12.1.20. Register Next ID Configuration 19 12.1.21. Register Trigger 12.1.22. Register Trigger Status 12.1.23. Register Error Configuration 12.1.24. Register Error Status
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide

10.4.1. Running the Hardware Test

Follow these steps to test the hardware design example on the System Console:

  • Open Tools ➤ System Debugging Tools ➤ System Console or type the command:

    system-console &

  • In the TCL Console window, type cd hwtest to change the directory to

    <design_example_dir>/hardware_test_design/hwtest.

  • Type source main_script.tcl to open a connection to the JTAG master and start the test.
  • Verify that the output of the TCL script matches the output from a sample test run, shown below.
  • Analyze the results. A successful run displays Test Passed in the System Console.
Figure 40. TCL Console 
% source main_script.tcl
JTAG Port ID       = 0
Power Up Variant   = 1GE_TSE

Start of DR test: 10/02/2025 12:03:18
Set JTAG Master Service Path

Warning: JTAG Master not found

Opened JTAG Master Service
Release DR controller reset
Wait for DR Ready....
Internal Serial Loopback not enabled.
Run test on startup profile (1GE_TSE):
BASE_ADDR=0x20000  TSE_PHY_BASE_ADDR is 131584
	 			Command Config  	 	 = 0x00000000
	 			Command Config  	 	 = 0x0000003b
	Run traffic test...
Startup test passed!
Assert tx/rx reset
Wait reset ack (assert) -----
Reset acknowledged
Setup DR reconfiguration: 1GE_TSE -> 10GE_nofec
Configuring DR Profile 10GE_nofec....
dr_ctrl_next_id_0_reg  0x80020001
Trigger DR interrupt
Wait for DR interrupt Ack....
DR Request acknowledged
Wait for DR reconfig to be done....
DR reconfig done, check for error
Deassert tx/rx reset
Wait reset ack (deassert) -----
Reset acknowledged
Run traffic test (10GE_nofec):
 RX PHY Register Access: Checking Clock Frequencies (KHz) 

      TXCLK 		:161140  (KHZ) 
      RXCLK 		:161140  (KHZ) 
Setting MR Soft CSR regster bit
	Run traffic test...
Assert tx/rx reset
Wait reset ack (assert) -----
Reset acknowledged
Setup DR reconfiguration: 10GE_nofec -> 10GE_fec
Configuring DR Profile 10GE_fec....
dr_ctrl_next_id_0_reg  0x80030002
Trigger DR interrupt
Wait for DR interrupt Ack....
DR Request acknowledged
Wait for DR reconfig to be done....
DR reconfig done, check for error
Deassert tx/rx reset
Wait reset ack (deassert) -----
Reset acknowledged
Run traffic test (10GE_fec):
 RX PHY Register Access: Checking Clock Frequencies (KHz) 

      TXCLK 		:161130  (KHZ) 
      RXCLK 		:161140  (KHZ) 
Setting MR Soft CSR regster bit
	Run traffic test...
Assert tx/rx reset
Wait reset ack (assert) -----
Reset acknowledged
Setup DR reconfiguration: 10GE_fec -> 1GE_TSE
Configuring DR Profile 1GE_TSE....
dr_ctrl_next_id_0_reg  0x80010003
Trigger DR interrupt
Wait for DR interrupt Ack....
DR Request acknowledged
Wait for DR reconfig to be done....
DR reconfig done, check for error
Deassert tx/rx reset
Wait reset ack (deassert) -----
Reset acknowledged
Run traffic test (1GE_TSE):
BASE_ADDR=0x20000  TSE_PHY_BASE_ADDR is 131584
	 			Command Config  	 	 = 0x0000003b
	 			Command Config  	 	 = 0x0000003b
	Run traffic test...
Test passed!
Closed JTAG Master Service
End of dr_test: 10/02/2025 12:04:02

DR Test Passed
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