GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 849710
Date 10/22/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application 5. Designing with the IP Core 6. Designing the IP Solution 7. Sharing Clocking and Applying SDC Constraints 8. Runtime Flow 9. Simulating the IP 10. Validating the IP 11. Appendix A: Functional Description 12. Registers 13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
1. Overview x
1.1. About the GTS Dynamic Reconfiguration Controller IP 1.2. About the Document 1.3. Key Concepts 1.4. System Level Block Diagram 1.5. IP Design Flow 1.6. Dynamic Reconfiguration 1.7. Design Considerations
1.1. About the GTS Dynamic Reconfiguration Controller IP x
1.1.1. Release Information 1.1.2. Features 1.1.3. High-Level Functional Overview 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training 1.2.6. GTS Dynamic Reconfiguration Target Applications
2. Quick Start Guide x
2.1. Steps to Generate and Run the Design Example 2.2. Steps to Create a Custom Dynamic Reconfiguration Design
2.1. Steps to Generate and Run the Design Example x
2.1.1. Generating the Design Example 2.1.2. Compiling the Design Example 2.1.3. Simulating the Design Example 2.1.4. Validating the Design Example
2.2. Steps to Create a Custom Dynamic Reconfiguration Design x
2.2.1. Simulating the Custom Design 2.2.2. Validating the Custom Design
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles 3.3. Generating HDL for Synthesis and Simulation 3.4. Using the HSSI Support Logic Assignment Editor 3.5. HSSI Support Logic Generation 3.6. Generating the Design Example 3.7. Compiling the Design Example
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles x
3.2.1. Configuring the IP
3.2.1. Configuring the IP x
3.2.1.1. Configuring the IP Parameters
3.4. Using the HSSI Support Logic Assignment Editor x
3.4.1. Quartus User Flow
3.4.1. Quartus User Flow x
3.4.1.1. IP List 3.4.1.2. Dynamic Reconfiguration Group List 3.4.1.3. Properties 3.4.1.4. DR Group Visualization Pane 3.4.1.5. Messages Pane
3.6. Generating the Design Example x
3.6.1. Generated Directory Structure and Files
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application x
4.1. Implementing Required Clocking 4.2. Implementing Required Resets 4.3. Implementing Required AVMM Interface 4.4. Control and Status Interface 4.5. Implementing Mux Selector Interface 4.6. Implementing SRC Interface 4.7. Implementing Local AVMM Interface
5. Designing with the IP Core x
5.1. Release Constraints 5.2. DR Design Guidelines
6. Designing the IP Solution x
6.1. Dynamic Reconfiguration QSF Settings 6.2. Defining DR Combinations 6.3. Instantiating the Generated DR Group 6.4. Generating and Instantiating the DR Controller
9. Simulating the IP x
9.1. Design Example Features 9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench 9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench 9.4. Simulating the GTS PTP/CPRI Multirate FPGA IP Design Example Testbench 9.5. Simulating the GTS Triple-Speed Ethernet (TSE)/Multirate Ethernet IP Design Example Testbench
9.1. Design Example Features x
9.1.1. Simulating the Testbench Flow
9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench x
9.2.1. Simulating the Design Example
9.2.1. Simulating the Design Example x
9.2.1.1. Verifying the Simulation Results
9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench x
9.3.1. Simulating the Design Example
9.3.1. Simulating the Design Example x
9.3.1.1. Verifying the Simulation Results
9.4. Simulating the GTS PTP/CPRI Multirate FPGA IP Design Example Testbench x
9.4.1. Simulating the Design Example
9.4.1. Simulating the Design Example x
9.4.1.1. Verifying the Simulation Results
9.5. Simulating the GTS Triple-Speed Ethernet (TSE)/Multirate Ethernet IP Design Example Testbench x
9.5.1. Simulating the Design Example
9.5.1. Simulating the Design Example x
9.5.1.1. Verifying the Simulation Results
10. Validating the IP x
10.1. Testing the Hardware Design Example for PMA Direct PHY Multirate 10.2. Testing the Hardware Design Example for Ethernet to CPRI 10.3. Testing the Hardware Design Example for PTP/CPRI Multirate 10.4. Testing the Hardware Design Example for TSE/Multirate Ethernet 10.5. Troubleshooting and Debugging Issues
10.1. Testing the Hardware Design Example for PMA Direct PHY Multirate x
10.1.1. Configure the Clocks in Hardware 10.1.2. Program the FPGA 10.1.3. Running the Hardware Test
10.2. Testing the Hardware Design Example for Ethernet to CPRI x
10.2.1. Running the Hardware Test
10.3. Testing the Hardware Design Example for PTP/CPRI Multirate x
10.3.1. Running the Hardware Test
10.4. Testing the Hardware Design Example for TSE/Multirate Ethernet x
10.4.1. Running the Hardware Test
11. Appendix A: Functional Description x
11.1. AVMM Clock Crossing Bridge 11.2. AVMM Decoder 11.3. Mux Sel, Local AVMM, and SRC Interface 11.4. Dynamic Reconfiguration CSR
12. Registers x
12.1. Configuration Registers 12.2. GTS Transceiver PHY Design Example: Registers 12.3. Ethernet to CPRI Design Example: Registers 12.4. PTP/CPRI Multirate Design Example: Registers 12.5. TSE/Multirate Ethernet Design Example: Registers
12.1. Configuration Registers x
12.1.1. Register Next ID Configuration 0 12.1.2. Register Next ID Configuration 1 12.1.3. Register Next ID Configuration 2 12.1.4. Register Next ID Configuration 3 12.1.5. Register Next ID Configuration 4 12.1.6. Register Next ID Configuration 5 12.1.7. Register Next ID Configuration 6 12.1.8. Register Next ID Configuration 7 12.1.9. Register Next ID Configuration 8 12.1.10. Register Next ID Configuration 9 12.1.11. Register Next ID Configuration 10 12.1.12. Register Next ID Configuration 11 12.1.13. Register Next ID Configuration 12 12.1.14. Register Next ID Configuration 13 12.1.15. Register Next ID Configuration 14 12.1.16. Register Next ID Configuration 15 12.1.17. Register Next ID Configuration 16 12.1.18. Register Next ID Configuration 17 12.1.19. Register Next ID Configuration 18 12.1.20. Register Next ID Configuration 19 12.1.21. Register Trigger 12.1.22. Register Trigger Status 12.1.23. Register Error Configuration 12.1.24. Register Error Status
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide

5.2. DR Design Guidelines

  1. The GTS Dynamic Reconfiguration Controller supports only one DR group. The DR Assignment Editor restricts designs to one DR group per controller, preventing the addition of multiple DR groups.
  2. If the GTS Dynamic Reconfiguration Controller is used in one profile, ensure it is consistently applied across all profiles.
  3. All lanes must be enabled for dynamic reconfiguration at startup combinations. This means you cannot disable a lane at startup and then use it for dynamic reconfiguration later.

    When creating the design, adhere to the following design rule check guidelines to ensure successful hardware testing, as these issues do not trigger errors during Quartus compilation:

    • Drive all clock ports; do not leave any floating. For instance, connect ports such as system_pll_clk pma_cu_clk_bank, and refclk.
    • Connect the corresponding ports of all protocol IPs used in the DR design to the respective ports of the GTS Reset Sequencer.
    • Ensure that the system_pll_clock frequency matches the protocol IP frequency at all times.
    • If an IP requires a lock signal, source it from the GTS System PLL clocks FPGA IP. For example, drive the Lock input with the lock output from the GTS System PLL clocks FPGA IP or HVIO PLL IP.
  4. Avalon® memory-mapped interface (AVMM interface) must be enabled for all protocol IPs on the same lane, or it must be disabled for all profiles on the same lane.
    Note: Enabling TTK/ETK is considered the same as enabling AVMM.
  5. The GTS Dynamic Reconfiguration Controller IP supports the GTS PMA/FEC Direct PHY IP, GTS CPRI PHY IP, GTS Ethernet Hard IP, Triple-Speed Ethernet FPGA IP, Serial Digital Interface II FPGA IP, and the Multi-Rate Ethernet PHY IP.
  6. The GTS Dynamic Reconfiguration Controller IP supports a maximum of 32 lanes.
  7. Only one System PLL is allowed per bank.
  8. In a design that uses Ethernet with PTP, startup profile must have PTP. In a quad with PTP, there can only be one instance of the Ethernet IP. PTP must be enabled for all profiles.
  9. Dynamic Reconfiguration designs do not allow switching between:
    1. Duplex and Simplex
    2. Tx Simplex and Rx Simplex (non-DS)
    3. Single-width and double-width

  10. Only one lane per quad can be enabled as “CDR Clk Out” to a pin, and every IP Profile on that lane must enable that pin.

    In DPHY, this is rx_cdr_divclk. In CPRI, this is “CDR clock output.” In Ethernet, this is “Dedicated CDR Clock output”.

    It is recommended to set that pin as a shared clock.

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