GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs
ID
849710
Date
8/11/2025
Public
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
3.1. Configuring the Quartus® Prime Pro Edition Project
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles
3.3. Generating HDL for Synthesis and Simulation
3.4. Using the Dynamic Reconfiguration Assignment Editor
3.5. Generating HSSI Dynamic Reconfiguration IP
3.6. Generating the Design Example
3.7. Compiling the Design Example
4.1. High-Level Interface Types
4.2. Dependent/Supporting IPs
4.3. Implementing Required Clocking
4.4. Implementing Required Resets
4.5. Implementing Required AVMM Interface
4.6. Control and Status Interface
4.7. Implementing Mux Selector Interface
4.8. Implementing SRC Interface
4.9. Implementing Local AVMM Interface
4.10. Connecting the Interfaces
4.11. Signal Functions
4.12. Integrating the IP With User Logic
4.13. Integrating the IP With Your Board
4.14. Integrating the IP on the Stack With a Software Driver
12.1.1. Register Next ID Configuration 0
12.1.2. Register Next ID Configuration 1
12.1.3. Register Next ID Configuration 2
12.1.4. Register Next ID Configuration 3
12.1.5. Register Next ID Configuration 4
12.1.6. Register Next ID Configuration 5
12.1.7. Register Next ID Configuration 6
12.1.8. Register Next ID Configuration 7
12.1.9. Register Next ID Configuration 8
12.1.10. Register Next ID Configuration 9
12.1.11. Register Next ID Configuration 10
12.1.12. Register Next ID Configuration 11
12.1.13. Register Next ID Configuration 12
12.1.14. Register Next ID Configuration 13
12.1.15. Register Next ID Configuration 14
12.1.16. Register Next ID Configuration 15
12.1.17. Register Next ID Configuration 16
12.1.18. Register Next ID Configuration 17
12.1.19. Register Next ID Configuration 18
12.1.20. Register Next ID Configuration 19
12.1.21. Register Trigger
12.1.22. Register Trigger Status
12.1.23. Register Error Configuration
12.1.24. Register Error Status
10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate
After successfully compiling the design example, configure it on the Agilex™ 5 device.
Figure 28. PMA Direct PHY Multirate Hardware Design Example Block Diagram
The gts_dr_ed_shim module instantiates a set of test control registers that drive the DUT interface signals.
The main_script.tcl TCL test program script controls all aspects of the test sequence through the jtag_avmm module. The jtag_avmm module accesses the test CSR registers and DR control registers by decoding incoming addresses. Once the reset is released, the test script polls the status of the DR IP and test CSR registers, controlling the test sequence by writing to these registers. It checks the RX data comparison results before and after the DR process is completed.