GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 849710
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application 5. Designing with the IP Core 6. Designing the IP Solution 7. Sharing Clocking and Applying SDC Constraints 8. Runtime Flow 9. Simulating the IP 10. Validating the IP 11. Appendix A: Functional Description 12. Registers 13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
1. Overview x
1.1. About the GTS Dynamic Reconfiguration Controller IP 1.2. About the Document 1.3. Key Concepts 1.4. System Level Block Diagram 1.5. Design Checklist 1.6. IP Design Flow 1.7. Dynamic Reconfiguration 1.8. Design Considerations 1.9. Design Migration Guidelines 1.10. Design Flow Requirements
1.1. About the GTS Dynamic Reconfiguration Controller IP x
1.1.1. Release Information 1.1.2. Features 1.1.3. High-Level Functional Overview 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training 1.2.6. GTS Dynamic Reconfiguration Target Applications
2. Quick Start Guide x
2.1. Steps to Generate and Run the Design Example 2.2. Steps to Create a Custom Dynamic Reconfiguration Design
2.1. Steps to Generate and Run the Design Example x
2.1.1. Generating the Design Example 2.1.2. Compiling the Design Example 2.1.3. Simulating the Design Example 2.1.4. Validating the Design Example
2.2. Steps to Create a Custom Dynamic Reconfiguration Design x
2.2.1. Simulating the Custom Design 2.2.2. Validating the Custom Design
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles 3.3. Generating HDL for Synthesis and Simulation 3.4. Using the Dynamic Reconfiguration Assignment Editor 3.5. Generating HSSI Dynamic Reconfiguration IP 3.6. Generating the Design Example 3.7. Compiling the Design Example
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles x
3.2.1. Configuring the IP
3.2.1. Configuring the IP x
3.2.1.1. Configuring the IP Presets 3.2.1.2. Configuring the IP Parameters
3.4. Using the Dynamic Reconfiguration Assignment Editor x
3.4.1. Quartus User Flow
3.4.1. Quartus User Flow x
3.4.1.1. IP List 3.4.1.2. Dynamic Reconfiguration Group List 3.4.1.3. Properties 3.4.1.4. DR Group Visualization Pane 3.4.1.5. Messages Pane
3.6. Generating the Design Example x
3.6.1. Generated Directory Structure and Files
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Implementing Required AVMM Interface 4.6. Control and Status Interface 4.7. Implementing Mux Selector Interface 4.8. Implementing SRC Interface 4.9. Implementing Local AVMM Interface 4.10. Connecting the Interfaces 4.11. Signal Functions 4.12. Integrating the IP With User Logic 4.13. Integrating the IP With Your Board 4.14. Integrating the IP on the Stack With a Software Driver
5. Designing with the IP Core x
5.1. Release Constraints 5.2. DR Design Guidelines
6. Designing the IP Solution x
6.1. Dynamic Reconfiguration QSF Settings 6.2. Defining DR Combinations 6.3. Instantiating the Generated DR Group 6.4. Generating and Instantiating the DR Controller
9. Simulating the IP x
9.1. Design Example Features 9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench 9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench
9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench x
9.2.1. Simulating the Design Example
9.2.1. Simulating the Design Example x
9.2.1.1. Simulating the Testbench Flow 9.2.1.2. Verifying the Simulation Results
9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench x
9.3.1. Simulating the Design Example
9.3.1. Simulating the Design Example x
9.3.1.1. Verifying the Simulation Results
10. Validating the IP x
10.1. List of Switches on the Developer Kit 10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate 10.3. Testing the Hardware Design Example for Ethernet to CPRI 10.4. Troubleshooting and Debugging Issues
10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate x
10.2.1. Configure the Clocks in Hardware 10.2.2. Program the FPGA 10.2.3. Running the Hardware Test
10.3. Testing the Hardware Design Example for Ethernet to CPRI x
10.3.1. Running the Hardware Test
11. Appendix A: Functional Description x
11.1. AVMM Clock Crossing Bridge 11.2. AVMM Decoder 11.3. Mux Sel, Local AVMM, and SRC Interface 11.4. Dynamic Reconfiguration CSR
12. Registers x
12.1. Configuration Registers 12.2. GTS Transceiver PHY Design Example: Registers 12.3. Ethernet to CPRI Design Example: Registers
12.1. Configuration Registers x
12.1.1. Register Next ID Configuration 0 12.1.2. Register Next ID Configuration 1 12.1.3. Register Next ID Configuration 2 12.1.4. Register Next ID Configuration 3 12.1.5. Register Next ID Configuration 4 12.1.6. Register Next ID Configuration 5 12.1.7. Register Next ID Configuration 6 12.1.8. Register Next ID Configuration 7 12.1.9. Register Next ID Configuration 8 12.1.10. Register Next ID Configuration 9 12.1.11. Register Next ID Configuration 10 12.1.12. Register Next ID Configuration 11 12.1.13. Register Next ID Configuration 12 12.1.14. Register Next ID Configuration 13 12.1.15. Register Next ID Configuration 14 12.1.16. Register Next ID Configuration 15 12.1.17. Register Next ID Configuration 16 12.1.18. Register Next ID Configuration 17 12.1.19. Register Next ID Configuration 18 12.1.20. Register Next ID Configuration 19 12.1.21. Register Trigger 12.1.22. Register Trigger Status 12.1.23. Register Error Configuration 12.1.24. Register Error Status
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide

2.2. Steps to Create a Custom Dynamic Reconfiguration Design

The following steps guide you through creating a custom design from scratch. While these steps reference the example design, including similar data rates and PLL configurations, they are intended to help you develop a design tailored to your specific requirements.
  1. Create a Quartus® Prime project.
    1. In the Quartus® Prime Pro Edition, click File ➤ New Project Wizard to create a new Quartus® Prime project. The wizard prompts you to specify a device.
    2. Specify the device family Agilex™ 5 (E-Series) and select the device that supports your design.
    3. Follow the on-screen instructions to complete the New Project creation.
  2. Configure the Dynamic Reconfiguration Controller IP.
    1. In the Quartus® Prime IP Catalog, locate the Dynamic Reconfiguration Controller IP.
    2. Configure the following dynamic reconfiguration controller parameters:
      • Nios® V Data Memory Size
      • Number of Transceiver Channels
      • Number of Supported Profiles
      • CSR Clock Frequency in MHz
  3. Generate the Dynamic Reconfiguration Controller IP.
  4. Configure the Protocol IPs.
    1. In the Quartus® Prime IP Catalog, locate the desired Protocol IP.
    2. Configure the IP to ensure certain settings are compatible between different instances, such as the system PLL.
      • Example - Setting System PLL:
        • Set the system PLL to 322.56 MHz for both instances
        • Set the PMA data rate to 9.8304 Gbps for one instance and 4.9152 Gbps for the other
      • Example - Configuring Ref Clocks:
        • Ref clocks can be shared between two different modes or use two different ref clocks
        • In the example design, IPs share the ref clocks with a frequency set to 156.25 MHz
      • Example - Setting Datapath Clocks: Set TX clkout to the System PLL clock divided by 2
  5. Include the protocol IPs and Dynamic Reconfiguration Controller IP in the Quartus® Prime project to create instances in new DR group.
  6. Generate the QSF assignments.
    1. In the main Quartus® Prime GUI, go to Assignments > Dynamic Reconfiguration (DR) Assignment Editor.
    2. In the DR Assignment Editor tool, select IPs from the IP list and create IP instances under IP combinations. The protocol name, IP direction, and width are listed for each IP. Specify relative offset, reconfiguration IDs, and combination IDs to match the desired combinations of IPs to be dynamically reconfigured.
    3. Change the name of the reconfiguration group. Here, dr_top is used as an example.
    4. Set Shared Clocks:
      • Enter shared clock settings explicitly for each IP instance.
      • Ensure the system PLL clock and lock inputs are shared.
    5. Generate reconfiguration groups.
      • Click Save Assignments button to save the assignments.
      • Review the generated QSF settings.
  7. Go to the Quartus Compilation dashboard and click HSSI Dynamic Reconfiguration IP generation button to generate the reconfiguration group RTL files (*.sv) and reconfiguration memory initialization files (*.mif).
  8. Instantiate the System PLL, Reset Sequencer IP, Generated reconfiguration group RTL, and GTS Dynamic Reconfiguration Controller IP in your project.
  9. For RTL connection examples, refer to the design examples provided in the GTS Dynamic Reconfiguration Design Example section.
  10. Incorporate the generated files into your project.
    1. Add the generated files from support_logic/dr_top/synth directory into your project. Ensure that you specify the path to these files, indicating that they reside in the support_logic/dr_top/synth directory.
    2. Add the dr_top.sv RTL file and the MIF file from the support_logic/dr_top/synth directory are included in the project.
  11. Instantiate the testbench components for demonstration.
    1. Refer to the design example for testbench components and scripts for simulation and hardware instantiation.
    2. Use the sim version of the MIF file and dr_top.sv file for simulation.
    3. Use the synth version of the MIF file and dr_top.sv file for synthesis.
  12. Compile your design.

Section Content
Simulating the Custom Design
Validating the Custom Design

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