General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

ID 847266
Date 4/07/2025
Public

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2.4.1.4. Single-Ended I/O Termination Implementation Guide

To implement I/O termination in your design, you can assign the termination for your pin using the Quartus® Prime Assignment Editor or through the External Memory Interfaces (EMIF) IP and PHY Lite for Parallel Interfaces Intel® FPGA IP.