General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs
ID
847266
Date
4/07/2025
Public
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1. Agilex™ 3 General-Purpose I/O Overview
2. Agilex™ 3 HSIO Banks
3. Agilex™ 3 HVIO Banks
4. Agilex™ 3 HPS I/O Banks
5. Agilex™ 3 SDM I/O Banks
6. Agilex™ 3 I/O Troubleshooting Guidelines
7. GPIO FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused HSIO Banks
2.5.14. HSIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for HSIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. Implementing a Pseudo Open Drain
2.5.20. Allowed Duration for Using RT OCT
2.5.21. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.22. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
2.4.1.4. Single-Ended I/O Termination Implementation Guide
To implement I/O termination in your design, you can assign the termination for your pin using the Quartus® Prime Assignment Editor or through the External Memory Interfaces (EMIF) IP and PHY Lite for Parallel Interfaces Intel® FPGA IP.
Section Content
Configuring OCT Using the Assignment Editor
OCT Features Assignment Names and Settings
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