General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

ID 847266
Date 8/04/2025
Public
Document Table of Contents

2.5.17. Maximum DC Current Restrictions

While using Agilex™ 3 HSIO pins, adhere to the maximum allowed duration of the per pin DC current limit.
Table 22.  Maximum Allowed Duration of DC Current Limit
DC Current Limit Maximum Allowed Duration (%)
±7.5 mA 100%
±10 mA 75%
±15 mA 50%
More than ±15 mA Not allowed