General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

ID 847266
Date 8/04/2025
Public
Document Table of Contents

2.5.10. Clocking Requirements

In your clocking scheme, use the dedicated clock pins for I/O PLL reference clock or as output clock for better jitter performance.

You must use the True Differential Signaling input standard for the I/O PLL reference clock.