General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

ID 847266
Date 8/04/2025
Public
Document Table of Contents

9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.08.04 25.1.1
  • Added new topic—Clock Restrictions for GPIO Interfaces.
  • Updated Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank.
  • Updated the note about VREF Sources and Input Standards Grouping.
  • Updated Unused Pins.
  • Updated the following IP names:
    • "Hard Processor System Agilex 3 FPGA IP" to "Hard Processor System FPGA IP"
    • "GPIO Intel® FPGA IP" to "GPIO FPGA IP".
  • Updated Table: GPIO FPGA IP Current Release Information.
2025.04.07 25.1 Initial release.