General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

ID 847266
Date 8/04/2025
Public

Visible to Intel only — GUID: sam1412835885407

Ixiasoft

Document Table of Contents

7.7. GPIO FPGA IP Timing

The performance of the GPIO IP depends on the I/O constraints and clock phases. To validate the timing for your GPIO configuration, Altera recommends that you use the Timing Analyzer.