General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

ID 847266
Date 8/04/2025
Public

Visible to Intel only — GUID: sam1412835880468

Ixiasoft

Document Table of Contents

7.4.1. Shared Signals

  • The input, output, and OE paths share the same clear and preset signals.
  • The output and OE path shares the same clock signals.