General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

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ID 847266
Date 8/04/2025
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 3 General-Purpose I/O Overview 2. Agilex™ 3 HSIO Banks 3. Agilex™ 3 HVIO Banks 4. Agilex™ 3 HPS I/O Banks 5. Agilex™ 3 SDM I/O Banks 6. Agilex™ 3 I/O Troubleshooting Guidelines 7. GPIO FPGA IP 8. Programmable I/O Features Description 9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs
1. Agilex™ 3 General-Purpose I/O Overview x
1.1. Package Selection and I/O Vertical Migration Support 1.2. Types of I/O Banks
2. Agilex™ 3 HSIO Banks x
2.1. HSIO Bank Overview 2.2. HSIO Features 2.3. HSIO Implementation Guide 2.4. HSIO Termination 2.5. HSIO Design Guidelines 2.6. HSIO Simulation
2.1. HSIO Bank Overview x
2.1.1. HSIO Bank Structure 2.1.2. HSIO Buffers and Registers
2.2. HSIO Features x
2.2.1. Supported I/O Standards for HSIO Banks 2.2.2. HSIO Buffer Behavior 2.2.3. Programmable I/O Element Features for the HSIO Bank
2.2.3. Programmable I/O Element Features for the HSIO Bank x
2.2.3.1. Guidelines: Programmable Output Slew Rate Control 2.2.3.2. Guidelines: Programmable Pull-Up Resistor 2.2.3.3. Guidelines: Programmable De-Emphasis
2.3. HSIO Implementation Guide x
2.3.1. I/O Assignments with the Quartus® Prime Assignment Editor 2.3.2. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
2.3.1. I/O Assignments with the Quartus® Prime Assignment Editor x
2.3.1.1. Assigning Pin I/O Standards in the Quartus® Prime Assignment Editor 2.3.1.2. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 2.3.1.3. HSIO Programmable IOE Features Assignment Names and Settings
2.4. HSIO Termination x
2.4.1. Single-Ended I/O Termination in Agilex™ 3 Devices 2.4.2. True Differential Signaling I/O Termination in Agilex™ 3 Devices
2.4.1. Single-Ended I/O Termination in Agilex™ 3 Devices x
2.4.1.1. Single-Ended I/O Standards On-Chip Termination 2.4.1.2. OCT Calibration Block 2.4.1.3. Single-Ended I/O Standards External Termination 2.4.1.4. Single-Ended I/O Termination Implementation Guide
2.4.1.1. Single-Ended I/O Standards On-Chip Termination x
2.4.1.1.1. RS OCT 2.4.1.1.2. RT OCT 2.4.1.1.3. Dynamic OCT
2.4.1.4. Single-Ended I/O Termination Implementation Guide x
2.4.1.4.1. Configuring OCT Using the Assignment Editor 2.4.1.4.2. OCT Features Assignment Names and Settings
2.4.2. True Differential Signaling I/O Termination in Agilex™ 3 Devices x
2.4.2.1. True Differential Signaling I/O Standard On-Chip Termination 2.4.2.2. True Differential Signaling I/O Standard External Termination
2.4.2.1. True Differential Signaling I/O Standard On-Chip Termination x
2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor 2.4.2.1.2. Guidelines: Differential Input RD OCT
2.5. HSIO Design Guidelines x
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os 2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank 2.5.3. VREF Sources and Input Standards Grouping 2.5.4. HSIO Pin Restrictions for External Memory Interfaces 2.5.5. RZQ Pin Requirement 2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.8. Simultaneous Switching Noise 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. Clock Restrictions for GPIO Interfaces 2.5.12. SDM Shared I/O Requirements 2.5.13. Unused Pins 2.5.14. VCCIO_PIO Supply for Unused HSIO Banks 2.5.15. HSIO Pins During Power Sequencing 2.5.16. Drive Strength Requirement for HSIO Input Pins 2.5.17. Maximum DC Current Restrictions 2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility 2.5.19. Connection to True Differential Signaling Input Buffers During Device Reconfiguration 2.5.20. Implementing a Pseudo Open Drain 2.5.21. Allowed Duration for Using RT OCT 2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction 2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
2.6. HSIO Simulation x
2.6.1. IBIS Models—HSIO Support 2.6.2. IBIS-AMI Models 2.6.3. HSPICE* Models 2.6.4. Net Length Reports
3. Agilex™ 3 HVIO Banks x
3.1. HVIO Bank Overview 3.2. HVIO Features 3.3. HVIO Implementation Guide 3.4. HVIO Design Guidelines 3.5. HVIO Simulation
3.1. HVIO Bank Overview x
3.1.1. HVIO Bank Structure 3.1.2. HVIO Buffers and Registers
3.2. HVIO Features x
3.2.1. Supported I/O Standards for HVIO Banks 3.2.2. Dedicated Features of HVIO Pins 3.2.3. HVIO Buffer Behavior 3.2.4. Programmable I/O Element Features for the HVIO Bank
3.2.4. Programmable I/O Element Features for the HVIO Bank x
3.2.4.1. Guidelines: Programmable Open-Drain Output
3.3. HVIO Implementation Guide x
3.3.1. I/O Assignments with the Quartus® Prime Assignment Editor 3.3.2. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
3.3.1. I/O Assignments with the Quartus® Prime Assignment Editor x
3.3.1.1. Assigning Pin I/O Standards in the Quartus® Prime Assignment Editor 3.3.1.2. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 3.3.1.3. HVIO Programmable IOE Features Assignment Names and Settings
3.4. HVIO Design Guidelines x
3.4.1. HVIO Pins During Power Sequencing 3.4.2. Unused HVIO Pins 3.4.3. VCCIO_HVIO Supply for Unused HVIO Banks 3.4.4. Maximum DC Current Restrictions
3.5. HVIO Simulation x
3.5.1. IBIS Models—HVIO Support 3.5.2. HSPICE* Models 3.5.3. Net Length Reports
4. Agilex™ 3 HPS I/O Banks x
4.1. HPS I/O Bank Overview 4.2. HPS I/O Features 4.3. HPS I/O Implementation Guide 4.4. HPS I/O Design Guidelines 4.5. HPS I/O Simulation
4.2. HPS I/O Features x
4.2.1. Supported I/O Standards for HPS I/O Banks 4.2.2. Programmable I/O Element Features for the HPS I/O Bank 4.2.3. HPS I/O Buffer Behavior
4.3. HPS I/O Implementation Guide x
4.3.1. Configuring Open Drain Feature for the HPS I/O 4.3.2. I/O Assignments with the Quartus® Prime Assignment Editor 4.3.3. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
4.3.2. I/O Assignments with the Quartus® Prime Assignment Editor x
4.3.2.1. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 4.3.2.2. HPS I/O Programmable IOE Features Assignment Names and Settings
4.4. HPS I/O Design Guidelines x
4.4.1. HPS I/O Pins During Power Sequencing 4.4.2. HPS Shared I/O Requirements
4.5. HPS I/O Simulation x
4.5.1. IBIS Models—HPS I/O Support 4.5.2. Net Length Reports
5. Agilex™ 3 SDM I/O Banks x
5.1. SDM I/O Bank Overview 5.2. SDM I/O Features 5.3. SDM I/O Design Guidelines 5.4. SDM I/O Simulation
5.2. SDM I/O Features x
5.2.1. Supported I/O Standards for SDM I/O Banks 5.2.2. SDM I/O Buffer Behavior 5.2.3. I/O Standards and Features for Configuration Pins
5.3. SDM I/O Design Guidelines x
5.3.1. SDM I/O Pins During Power Sequencing 5.3.2. Avalon® Streaming Interface Dedicated Configuration Pins
5.4. SDM I/O Simulation x
5.4.1. IBIS Models—SDM I/O Support 5.4.2. Net Length Reports
7. GPIO FPGA IP x
7.1. Release Information for GPIO FPGA IP 7.2. Generating the GPIO FPGA IP 7.3. GPIO FPGA IP Parameter Settings 7.4. GPIO FPGA IP Interface Signals 7.5. GPIO FPGA IP Architecture 7.6. Verifying Resource Utilization and Design Performance 7.7. GPIO FPGA IP Timing 7.8. GPIO FPGA IP Design Examples
7.2. Generating the GPIO FPGA IP x
7.2.1. Altera® FPGA IP Generation Output
7.3. GPIO FPGA IP Parameter Settings x
7.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP
7.4. GPIO FPGA IP Interface Signals x
7.4.1. Shared Signals 7.4.2. Data Bit-Order for Data Interface 7.4.3. Input and Output Bus High and Low Bits 7.4.4. Data Interface Signals and Corresponding Clocks
7.5. GPIO FPGA IP Architecture x
7.5.1. GPIO FPGA IP Data Paths 7.5.2. Register Packing
7.5.1. GPIO FPGA IP Data Paths x
7.5.1.1. Input Path 7.5.1.2. Output and Output Enable Paths
7.7. GPIO FPGA IP Timing x
7.7.1. Timing Components 7.7.2. Delay Elements 7.7.3. Timing Analysis 7.7.4. Timing Closure Guidelines
7.7.3. Timing Analysis x
7.7.3.1. Single Data Rate Input Register 7.7.3.2. DDIO Input Register 7.7.3.3. Single Data Rate Output Register 7.7.3.4. DDIO Output Register
7.8. GPIO FPGA IP Design Examples x
7.8.1. GPIO FPGA IP Synthesizable Quartus® Prime Design Example 7.8.2. GPIO FPGA IP Simulation Design Example
8. Programmable I/O Features Description x
8.1. Programmable Pre-Emphasis 8.2. Programmable De-Emphasis 8.3. Programmable Differential Output Voltage 8.4. Continuous Time Linear Equalization
1. Agilex™ 3 General-Purpose I/O Overview
2. Agilex™ 3 HSIO Banks
3. Agilex™ 3 HVIO Banks
4. Agilex™ 3 HPS I/O Banks
5. Agilex™ 3 SDM I/O Banks
6. Agilex™ 3 I/O Troubleshooting Guidelines
7. GPIO FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 3 FPGAs and SoCs

7.3. GPIO FPGA IP Parameter Settings

You can set the parameter settings for the GPIO FPGA IP in the Quartus® Prime software. There are three groups of options: General, Buffer, and Registers.
Table 52.   GPIO FPGA IP Parameters—General
Parameter Condition Allowed Values Description
Data Direction —
  • Input
  • Output
  • Bidir

Specifies the data direction for the GPIO.
Data width —

1 to 128

Specifies the data width.
Use legacy top-level port names —
  • On
  • Off

Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices.

For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l.

Note: The behavior of these ports are different than in the Stratix® V, Arria® V, and Cyclone® V devices. For the migration guideline, refer to the related information.
Table 53.   GPIO IP Parameters—Buffer
Parameter Condition Allowed Values Description
Use differential buffer —
  • On
  • Off

If turned on, enables differential I/O buffers.
Use pseudo differential buffer
  • Data Direction = Output
  • Use differential buffer = On
  • On
  • Off

If turned on in output mode, enables pseudo differential output buffers.

This option is automatically turned on for bidirectional mode if you turn on Use differential buffer.
Enable output enable port Data Direction = Output
  • On
  • Off

If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.
Table 54.   GPIO IP Parameters—Registers
Parameter Condition Allowed Values Description
Register mode —
  • None
  • Simple register
  • DDIO

Specifies the register mode for the GPIO IP:

  • None—specifies a simple wire connection from/to the buffer.
  • Simple register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
  • DDIO— specifies that the IP core uses the DDIO.
Enable synchronous clear / preset port Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement synchronous reset port.

  • None—Disables synchronous reset port.
  • Clear—Enables the SCLR port for synchronous clears.
  • Preset—Enables the SSET port for synchronous preset.
Enable asynchronous clear / preset port Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement asynchronous reset port.

  • None—Disables asynchronous reset port.
  • Clear—Enables the ACLR port for asynchronous clears.
  • Preset—Enables the ASET port for asynchronous preset.

ACLR and ASET signals are active high.
Enable clock enable ports Register mode = DDIO
  • On
  • Off
  • On—exposes the clock enable (CKE) port to allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
  • Off—clock enable port is not exposed and data always pass through the register automatically.
Input DDIO With Delay
  • Data Direction = Bidir
  • Register mode = DDIO
  • On
  • Off
 If turned on, the I/O uses the DDIO with delay.
Separate input/output Clocks
  • Data Direction = Bidir
  • Register mode = Simple register or DDIO
  • On
  • Off
 If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode.

Section Content
Guideline: Swap datain_h and datain_l Ports in Migrated IP

Related Information
Level Two Title