Cyclone® V SoC Development Kit User Guide

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ID 830285
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Update Portal 5. Board Test System 6. Document Revision History for the Cyclone® V SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting Up the Development Kit 3.2. Factory Default Switch and Jumper Settings 3.3. Restoring the MAX® V CPLD to the Factory Setting 3.4. Restoring CFI Flash Device to the Factory Defaults
3.2. Factory Default Switch and Jumper Settings x
3.2.1. Restoring the Default Settings for Power Solution 2 Board 3.2.2. Restoring the Default Settings for Power Solution 1 Board
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page
5. Board Test System x
5.1. Preparing the Board for the Board Test System 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. The Power Monitor 5.5. The Clock Control 5.6. Configuring the FPGA Using the Quartus® Prime Programmer
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab Board Information JTAG Chain 5.3.3. The GPIO Tab 5.3.4. The I2C Tab 5.3.5. The DDR3 Tab 5.3.6. The SDI Video Tab 5.3.7. The HSMC Tab
5.6. Configuring the FPGA Using the Quartus® Prime Programmer x
5.6.1. Before Configuring 5.6.2. Configuring the FPGA
A. Development Kit Components x
A.1. Board Overview A.2. Programming Flash Memory A.3. Power
A.2. Programming Flash Memory x
A.2.1. CFI Flash Memory A.2.2. quad SPI Flash Memory A.2.3. SD Card Memory
A.2.1. CFI Flash Memory x
A.2.1.1. CFI Flash Memory Map A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer A.2.1.3. Converting .sof Files to a .pof
A.2.2. quad SPI Flash Memory x
A.2.2.1. Programming quad SPI Flash Using the Quartus® Prime Programmer
A.2.3. SD Card Memory x
A.2.3.1. Programming the SD Card Boot Image
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Update Portal
5. Board Test System
6. Document Revision History for the Cyclone® V SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

5.3.2. The System Info Tab

The System Info tab shows information about the board's current configuration. The tab displays the content of the MAX® V registers, the JTAG chain, the board's MAC address, the flash memory map, and other details stored on the board.
Figure 9. The System Info Tab

The following sections describe the controls on the System Info tab.

Board Information

The Board information control displays static information about your board.

  • Board Name: Indicates the official name of the board.
  • Part number: Indicates the part number of the board.
  • Serial number: Indicates the serial number of the board.
  • Factory test version: Indicates the version of the Board Test System currently running on the board.
  • MAC1: Indicates the MAC address of the board's ENET1 10/100 port.
  • MAC2: Indicates the MAC address of the board's ENET2 10/100 port.
  • HPS MAC1: Indicates the MAC address of the board's HPS 10/100/1000 Ethernet port.
  • MAX V ver: Indicates the version of MAX V code currently running on the board. The MAX V code resides in the cycloneVSX_5csxfc6df31_soc\examples directory. Newer revisions of this code might be available on the Cyclone® V SoC Development Kit webpage of the Intel website.

JTAG Chain

The JTAG chain control shows all the devices currently in the JTAG chain. The Cyclone® V device is always the first device in the chain. The JTAG chain is normally mastered by the onboard Intel® FPGA Download Cable II.
Note: If you plug in an external onboard Intel® FPGA Download Cable cable to the JTAG header (J23), the onboard Intel® FPGA Download Cable II is disabled.
Note: JTAG DIP switch bank (SW4) selects which interfaces are in the chain. Refer to the SW4 JTAG DIP Switch Settings table in the Factory Default Switch and Jumper Settings section for detailed settings.

For details on the JTAG chain, refer to the Cyclone® V SoC Development Board Reference Manual . For Intel® FPGA Download Cable II configuration details, refer to the Cable and Adapter Drivers Information webpage of the Intel website.

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