Cyclone® V SoC Development Kit User Guide

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ID 830285
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Update Portal 5. Board Test System 6. Document Revision History for the Cyclone® V SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting Up the Development Kit 3.2. Factory Default Switch and Jumper Settings 3.3. Restoring the MAX® V CPLD to the Factory Setting 3.4. Restoring CFI Flash Device to the Factory Defaults
3.2. Factory Default Switch and Jumper Settings x
3.2.1. Restoring the Default Settings for Power Solution 2 Board 3.2.2. Restoring the Default Settings for Power Solution 1 Board
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page
5. Board Test System x
5.1. Preparing the Board for the Board Test System 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. The Power Monitor 5.5. The Clock Control 5.6. Configuring the FPGA Using the Quartus® Prime Programmer
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The I2C Tab 5.3.5. The DDR3 Tab 5.3.6. The SDI Video Tab 5.3.7. The HSMC Tab
5.6. Configuring the FPGA Using the Quartus® Prime Programmer x
5.6.1. Before Configuring 5.6.2. Configuring the FPGA
A. Development Kit Components x
A.1. Board Overview A.2. Programming Flash Memory A.3. Power
A.2. Programming Flash Memory x
A.2.1. CFI Flash Memory A.2.2. quad SPI Flash Memory A.2.3. SD Card Memory
A.2.1. CFI Flash Memory x
A.2.1.1. CFI Flash Memory Map A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer A.2.1.3. Converting .sof Files to a .pof
A.2.2. quad SPI Flash Memory x
A.2.2.1. Programming quad SPI Flash Using the Quartus® Prime Programmer
A.2.3. SD Card Memory x
A.2.3.1. Programming the SD Card Boot Image
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Update Portal
5. Board Test System
6. Document Revision History for the Cyclone® V SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer

You can use the JTAG interface in Altera® CPLDs to indirectly program the flash memory device. The Altera® CPLD JTAG block interfaces directly with the logic array in a special JTAG mode.
This mode brings the JTAG chain through the logic array instead of the Altera® CPLD boundary-scan cells (BSC). The Parallel Flash Loader Intel® FPGA IP provides JTAG interface logic to do the following:
  • Convert the JTAG stream provided by the Quartus® Prime software.
  • Program the CFI flash memory devices connected to the CPLD I/O pins.
Programming the CFI Flash Memory With the JTAG InterfaceShows an Altera® CPLD configured as a bridge to program the CFI flash memory device through the JTAG interface.

Perform the following steps to program a user design to the flash device in the Quartus® Prime Programmer:

Note: The following flash writing procedure blinks the SEL 2, 1, and 0 LEDs and does not support the Power Monitor, Clock Control, or other logic functions.
  1. On the Tools menu in the Quartus® Prime software, click Programmer.
  2. In the Programmer window, click Auto-Detect.
    Note: If you do not see Intel® FPGA Download Cable or the board's embedded Intel® FPGA Download Cable II listed next to Hardware Setup, refer to the Cable and Adapter Drivers Information webpage in the Intel website.
  3. Click Add File and open cycloneVSX_5csxfc6df31_soc\factory_recovery\max2_PFL_writer.pof .
  4. Turn on the Program/Configure option for the .pof file.
  5. Click Start to download the selected configuration file to the MAX® V CPLD. Configuration is complete when the progress bar reaches 100%.
  6. Click Auto Detect and a flash device should show up attached to the MAX® V in the main window.
  7. Double-click the graphic of the flash device in the device chain pane to display the Device's Properties dialog box.
  8. Select the flash image .pof file generated from the Quartus® Prime Convert Programming Files dialog box. The default file name is output_file.pof .
  9. After the flash image .pof is attached in the Quartus® Prime Programmer, turn on Page_1 and Option Bits. (Page_0 is reserved for the GSRD factory design.)
  10. Click Start.
  11. After the flash writing process has completed, power cycle the board and look for the MAX CONF DONE LED to turn ON if the writing process is successful.
  12. Altera recommends that you return to the MAX® V System Controller factory design after completing the flash writing. To do so, program the MAX® V with cycloneVSX_5csxfc6df31_soc\factory_recovery\max<version>.pof . For more information refer to the Restoring the MAX® V CPLD to the Factory Settings section.
    For more information on programming flash memory, refer to the Parallel Flash Loader Intel® FPGA IP User Guide and Using FPGA-Based Parallel Flash Loader with the Quartus® Prime Software.
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