Cyclone® V SoC Development Kit User Guide

Download PDF
ID 830285
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Update Portal 5. Board Test System 6. Document Revision History for the Cyclone® V SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting Up the Development Kit 3.2. Factory Default Switch and Jumper Settings 3.3. Restoring the MAX® V CPLD to the Factory Setting 3.4. Restoring CFI Flash Device to the Factory Defaults
3.2. Factory Default Switch and Jumper Settings x
3.2.1. Restoring the Default Settings for Power Solution 2 Board 3.2.2. Restoring the Default Settings for Power Solution 1 Board
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page
5. Board Test System x
5.1. Preparing the Board for the Board Test System 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. The Power Monitor 5.5. The Clock Control 5.6. Configuring the FPGA Using the Quartus® Prime Programmer
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The I2C Tab 5.3.5. The DDR3 Tab 5.3.6. The SDI Video Tab 5.3.7. The HSMC Tab
5.6. Configuring the FPGA Using the Quartus® Prime Programmer x
5.6.1. Before Configuring 5.6.2. Configuring the FPGA
A. Development Kit Components x
A.1. Board Overview A.2. Programming Flash Memory A.3. Power
A.2. Programming Flash Memory x
A.2.1. CFI Flash Memory A.2.2. quad SPI Flash Memory A.2.3. SD Card Memory
A.2.1. CFI Flash Memory x
A.2.1.1. CFI Flash Memory Map A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer A.2.1.3. Converting .sof Files to a .pof
A.2.2. quad SPI Flash Memory x
A.2.2.1. Programming quad SPI Flash Using the Quartus® Prime Programmer
A.2.3. SD Card Memory x
A.2.3.1. Programming the SD Card Boot Image
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Update Portal
5. Board Test System
6. Document Revision History for the Cyclone® V SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

5.4. The Power Monitor

The Power Monitor measures and reports current power information. To start the application, click Power Monitor in the Board Test System application.
Attention: You can also run the Power Monitor as a stand-alone application. PowerMonitor.bat resides in the cycloneVSX_5csxfc6df31_soc\examples\board_test_system directory.

The Power Monitor communicates with the MAX® V device on the board through the JTAG bus. A power monitor circuit attached to the MAX® V device allows you to measure the power that the Cyclone® V FPGA is consuming.

Attention: The Power Monitor measures power over an I2C bus with multiple masters. You might see some glitches in the measurements if the HPS is booted. The GSRD and other Linux images access the I2C bus periodically and cause inaccurate measurements for a cycle or two. These should go away and likely return to an accurate, steady state measurement for most designs.
Figure 15. The Power Monitor

The following sections describe the Power Monitor controls.

U34 and U26

The U34 and U26 groups show the power rail graphs. They display the mA power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset.

Attention: You can enlarge a graph by clicking on it. Click it again to restore the original size.
  • Temp on 2978: The temperature controls display only the temperature from the power supply manager, not the FPGA.
  • Total Power: These controls display the sum of all four rails for each group, U34 and for U26.

Controls

This group contains the following controls:

  • Start: Starts the communication with the board to monitor power.
  • Stop: Stops the communication with the board to monitor power.
  • Update speed: Specifies how often to refresh the graph.
  • Log Results: Specifies that a log file is saved to cycloneVSX_5csxfc6df31_soc\examples\board_test_system .
  • MAX V version—Indicates the version of MAX® V code currently running on the board. The MAX® V code resides in the following directories:
    • cycloneVSX_5csxfc6df31_soc\factory_recovery
    • cycloneVSX_5csxfc6df31_soc\examples\max5

A table with the power rail information is available in the Cyclone® V SoC Development Board Reference Manual.

Related Information
Level Two Title