Cyclone® V SoC Development Kit User Guide

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ID 830285
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Update Portal 5. Board Test System 6. Document Revision History for the Cyclone® V SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Standard Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting Up the Development Kit 3.2. Factory Default Switch and Jumper Settings 3.3. Restoring the MAX® V CPLD to the Factory Setting 3.4. Restoring CFI Flash Device to the Factory Defaults
3.2. Factory Default Switch and Jumper Settings x
3.2.1. Restoring the Default Settings for Power Solution 2 Board 3.2.2. Restoring the Default Settings for Power Solution 1 Board
4. Board Update Portal x
4.1. Connecting to the Board Update Portal Web Page
5. Board Test System x
5.1. Preparing the Board for the Board Test System 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. The Power Monitor 5.5. The Clock Control 5.6. Configuring the FPGA Using the Quartus® Prime Programmer
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The I2C Tab 5.3.5. The DDR3 Tab 5.3.6. The SDI Video Tab Pattern Generator Intensity SDI Standard Data Test 5.3.7. The HSMC Tab
5.6. Configuring the FPGA Using the Quartus® Prime Programmer x
5.6.1. Before Configuring 5.6.2. Configuring the FPGA
A. Development Kit Components x
A.1. Board Overview A.2. Programming Flash Memory A.3. Power
A.2. Programming Flash Memory x
A.2.1. CFI Flash Memory A.2.2. quad SPI Flash Memory A.2.3. SD Card Memory
A.2.1. CFI Flash Memory x
A.2.1.1. CFI Flash Memory Map A.2.1.2. Programming CFI Flash Using the Quartus® Prime Programmer A.2.1.3. Converting .sof Files to a .pof
A.2.2. quad SPI Flash Memory x
A.2.2.1. Programming quad SPI Flash Using the Quartus® Prime Programmer
A.2.3. SD Card Memory x
A.2.3.1. Programming the SD Card Boot Image
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Update Portal
5. Board Test System
6. Document Revision History for the Cyclone® V SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

5.3.6. The SDI Video Tab

The SDI Video tab allows you to test the SDI video interface on your board.
Figure 13. The SDI Video Tab

The following sections describe the controls on the SDI Video tab.

Pattern Generator

This control specifies the test pattern to output to the monitor. The following choices are available:

  • Color bar: Specifies a video color bar pattern with eight vertical color bars as shown in table below.
    Table 12.  HDMI Color Bar Test Pattern
    Color Bar Color RGB Values
    White/Grey 180,180,180
    Yellow 180,180,16
    Cyan 16,180,180
    Green 16,180,16
    Magenta 180,16,180
    Red 180,16,16
    Blue 16,16,180
    Black 16,16,16
  • Pathological: Specifies a video color bar pattern with two horizontal color bars that stresses the receive PLL.
  • PRBS: Specifies a pseudo-random bit sequence useful for electrical testing of the interface for data integrity.

Intensity

Specifies the color intensity of the transmitted color bar pattern. The following choices are available.

  • 75%: Specifies 75% intensity.
  • 100%: Specifies 100% intensity.

SDI Standard

Specifies the video standard used by the pattern generator on the SDI video stream. The following choices are available:

  • SD: Specifies a 270 Mbps data rate.
  • HD: Specifies a 1.485 Gbps data rate.
  • 3G HD: Specifies a 2.97 Gbps data rate.

Data Test

This group displays information about the SDI interface test when running in PRBS mode in the patter generator

  • Data rate: Displays the current SDI data rate in megabytes per second (MBps).
  • Freq: Displays the data rate frequency in MHz which is equivalent to Mbps.
  • Bits:Displays the number of bits transmitted since clicking Start.
  • Inserted errors: Displays the number of errors inserted by clicking Insert Error button.
  • Detected errors: Displays the number of bit errors detected by the error checking circuitry.
  • BER: Displays the bit error rate of the interface.
  • PLL lock: Displays Yes if the SDI PLL is locked.
  • Pattern Sync: Displays Yes if the receiver has detected the input data pattern.
  • Start: Starts the PRBS data test and begins to monitor and update screen with live test results.
  • Stop: Stops the PRBS data test.
  • Insert Error: Inserts an error into an SDI data stream that is detected by the receiver when in loopback using the included video cable.
  • Clear: Clears the Detected errors counter.
  • PMA Setting: Opens the PMA settings window that allows for adjusting the analog transceiver settings, such as output voltage, loopback settings, and equalization.
  • PRBS (list): Selects the transmit pattern and sets the receive error detection circuitry to expect the same pattern for use in loopback testing.
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