Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

ID 823097
Date 7/08/2024
Public

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Document Table of Contents

2. Introduction

Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.

The Scalable Scatter-Gather DMA Intel® FPGA IP (SSGDMA) is a low-footprint multiport direct memory access (DMA), which enables high bandwidth DMA when paired with a mixture of Avalon-ST, AXI-ST (one direction) and AXI-4 (bidirectional) peripherals. The SSGDMA IP supports up to 8 device ports, with each ST device port supporting one DMA channel in one direction, and each MM device port supporting one bidirectional DMA channel.

In DMA PCIe mode, you can use the SSGDMA IP with GTS AXI Streaming Intel® FPGA IP for PCI Express. The SSGDMA IP arbitrates the data between a host and multiple device ports.

In DMA SoC mode, the SSGDMA IP is equipped with AXI-4 interfaces which is paired with HPS or Nios® V processor.

Figure 1.  Scalable Scatter-Gather DMA Intel® FPGA IP Overview Diagram