Scalable Scatter-Gather DMA Intel® FPGA IP User Guide

ID 823097
Date 4/07/2025
Public
Document Table of Contents

3.2. DMA SoC Mode

In this mode, the SSGDMA is paired with the HPS/ Nios® V Processor. The host AXI4 interface is accessing to host memory from HPS or Nios® V for both descriptor and data.

The host interface supports the HPS F2S/F2SDRAM interface requirement for cache coherency and security access. The cache coherency and security access are only applicable to the F2S interface from HPS only.

There is a host_csr AXI4-Lite interface available for the host to access the control and status register.

Note: For all AXI4 transactions sent to the user logic, the fixed identification tag number must be used to avoid out-of-order responses returned as Host Agent currently does not support reordering.