3.1.1.1. PCIe* TLP Constructor
3.1.1.2. PCIe* TLP ID Generation
3.1.1.3. PCIe TX Credit Controller
3.1.1.4. PCIe* TX Scheduler
3.1.1.5. PCIe TLP Completer
3.1.1.6. PCIe RX Router
3.1.1.7. PCIe* MSI-X Controller
3.1.1.8. PCIe BAR0
3.1.1.9. PCIe Bursting Manager (BAM)
3.1.1.10. Completion Timeout Parser
3.1.1.11. Control Shadow Parser
4.2.1. Application Packet Receive Interface
4.2.2. Application Packet Transmit Interface
4.2.3. Control Shadow Interface
4.2.4. Transmit Flow Control Credit Interface
4.2.5. Completion Timeout Interface
4.2.6. PCIe* Miscellaneous Signals
4.2.7. Control and Status Register Responder Manager Interface
4.2.8. Bursting Manager Interface
3.2. DMA SoC Mode
In this mode, the SSGDMA is paired with the HPS/ Nios® V Processor. The host AXI4 interface is accessing to host memory from HPS or Nios® V for both descriptor and data.
The host interface supports the HPS F2S/F2SDRAM interface requirement for cache coherency and security access. The cache coherency and security access are only applicable to the F2S interface from HPS only.
There is a host_csr AXI4-Lite interface available for the host to access the control and status register.
Note: For all AXI4 transactions sent to the user logic, the fixed identification tag number must be used to avoid out-of-order responses returned as Host Agent currently does not support reordering.
Related Information