GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 817713
Date 5/15/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.8. Running the Design Example

Table 4.  Test Operations Supported by the GTS AXI Streaming Intel IP for PCI Express* Design Example
Operations Required BAR

Supported by GTS AXI Streaming Intel IP for PCI Express* PIO Design Examples

0: Link test - 64 writes and reads

0 Yes

1: Write memory space

0 Yes

2: Read memory space

0 Yes

3: Write configuration space

N/A Yes

4: Read configuration space

N/A Yes

5: Change BAR for PIO

N/A No

6: Change device

N/A No

7: Enable SR-IOV

N/A No

8: Do a link test for every enabled virtual function belonging to the current device

N/A No

9: Perform DMA for Throughput

0 No

10: Quit program

N/A Yes