GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/15/2025
Public
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A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
1.2.2.4. Completion Module
When both Completion command from the Read Write module and read data from the Avalon® memory-mapped interface are available, the Completion state machine captures the information.
The Completion command is stored in the Completion command FIFO. The read data is stored in Aligned Completion Data Buffer after being shifted by the Barrel Shifter. The stored Completion command and read data is shifted to the PCIe* upstream through TX Completion.