GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 817713
Date 5/15/2025
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Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description 1.3. Performance Design Example 1.4. Performance Design Example Functional Description
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks Intel® FPGA IP 1.2.5. GTS Reset Sequencer Intel® FPGA IP 1.2.6. Reset Release Intel® FPGA IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. TX Credit Initialization 1.2.2.7. AXI to Avalon® Streaming Interface Adapter 1.2.2.8. Soft Reset Controller
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSim* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench 2.4.4. Performance Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.8. Running the Design Example x
2.8.1. Running the PIO Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
A. Appendix

3. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.05.15 25.1 8.0.0 Made the following change:
  • Updated the hardware support column for the Gen3x1 Interface 128-bit Endpoint mode PIO design example in the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Examples table.
2025.04.07 25.1 8.0.0 Made the following changes:
  • Updated the About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example section with support information about Agilex™ 3 FPGAs.
  • Updated the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Examples table with Performance design example.
  • Updated the Programmed Input/Output Design Example section with support information about Agilex™ 3 FPGAs and supported PLD clock frequencies.
  • Updated the Programmed Input/Output Design Example Functional Description section with a figure for the PIO Design Example ( PCIe* 3.0 x4/x1 Variant).
  • Updated the TX Credit Initialization topic in PIO Application section.
  • Added new topic Soft Reset Controller in PIO Application section.
  • Updated the GTS System PLL Clocks Intel® FPGA IP topic with support information about Agilex™ 3 FPGAs.
  • Added new sections Performance Design Example and Performance Design Example Functional Description.
  • Updated the Quick Start Guide section with information about the Performance design example.
  • Updated the Directory Structure for the GTS AXI Streaming Intel FPGA IP for PCI Express Design Example figure in the Directory Structure section.
  • Updated the Generating the Design Example section with information about the Performance design example and Agilex™ 3 FPGAs.
  • Updated the notes about FASTSIM and PIPE mode in the Simulating the Design Example section.
  • Updated the run command in step 2 in the Running VCS* MX Simulation in Interactive Mode section.
  • Added new section Performance Design Example Testbench.
  • Updated the note about PIPE mode in the Compiling the Design Example section.
  • Updated the Hardware and Software Requirements section for Quartus® Prime Pro Edition software version 25.1.
2025.01.24 24.3.1 7.0.0 Made the following changes:
  • Updated the GTS AXI Streaming Intel FPGA IP for PCI Express table with a new Gen4x8 Interface 512-bit Endpoint PIO example.
  • Updated the Programmed Input/Output Design Example section with the PCIe* 4.0 x8 design example.
  • Updated the Programmed Input/Output Design Example Functional Description section with new figure for the PCIe* 4.0 x8 PIO design example.
  • Removed the i_gpio_perst0_n connection requirements in the GTS AXI Streaming IP—Design Under Test (DUT) topic in the PIO Application section.
  • Removed the frequency requirements and added the 512-bit PIO design example information in the Width Adapter topic in the PIO Application section.
  • Updated the figure in the Directory Structure section with new folder names and a file.
  • Updated the Example Designs Tab figure and removed a note in the Generating the Design Example section.
  • Updated simulation script directory and the notes for FASTSIM + PIPE mode in the Simulating the Design Example section.
  • Updated the working directory and simulation command in the Steps to Run Simulation using VCS* MX section.
  • Updated the simulation command in the Running VCS* MX Simulation in Interactive Mode section.
  • Updated the working directory and simulation command in the Steps to Run Simulation using QuestaSim* section.
  • Updated the working directory and simulation command in the Steps to Run Simulation using Xcelium* section.
  • Updated the working directory and simulation command in the Steps to Run Simulation using Riviera-PRO* section.
  • Updated the PIO Design Example Simulation Testbench figure with the PCIe* x8 link in the Design Example Simulation Testbench section.
2024.11.04 24.3 6.0.0 Made the following changes:
  • Updated the About the GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example section with a new Gen3x4 Interface 128-bit Endpoint PIO example.
  • Updated the figure title in the Programmed Input/Output Design Example section.
  • Updated the steps and added development kit information in the Generating the Design Example section.
  • Added a note about how to enable FASTSIM + PIPE mode in the Simulating the Design Example section.
  • Removed the Steps to Run Simulation using VCS* section.
  • Updated the Steps to Run Simulation using VCS* MX section with the FASTSIM + PIPE mode simulation command.
  • Updated the Steps to Run Simulation using QuestaSim* section with the FASTSIM + PIPE mode simulation command.
  • Added new section Steps to Run Simulation using Xcelium* .
  • Added new section Steps to Run Simulation using Riviera-PRO* .
  • Updated the figure title in the Design Example Simulation Testbench section.
  • Added new topic Root Port BFM in the Design Example Simulation Testbench section.
  • Added a note about design compilation with PIPE mode in the Compiling the Design Example section.
  • Added new section Hardware and Software Requirements.
  • Added new section Installing the Linux Kernel Driver.
  • Added new section Running the Design Example with new topic Running the PIO Design Example.
  • Added new Appendix A.1. BFM Procedures and Functions.
2024.05.09 24.1 4.0.0 Initial release.
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