GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/15/2025
Public
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A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
A.1.11.5. ebfm_log_open Verilog HDL Function
The ebfm_log_open procedure opens a log file of the specified name. All displayed messages are called by ebfm_display and are written to this log file as simulator standard output.
Location |
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Syntax |
ebfm_log_open (fn) | |
Argument |
fn | This argument is type string and provides the file name of log file to be opened. |