GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/15/2025
Public
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A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
2.5. Compiling the Design Example
- In the Quartus® Prime software, navigate to <project_dir>/intel_pcie_gts_0_example_design/ and open the design example project file (pcie_ed.qpf).
- On the Processing menu, select Start Compilation to compile the design example project.
Note: Design example compilation is not supported when you enable the Enable PIPE Mode Simulation parameter setting in the System Settings tab of the IP Parameter Editor GUI. PIPE mode simulation for the design example is supported when you enable the Enable PIPE Mode Simulation parameter setting in the Example Designs tab of the IP Parameter Editor GUI.
- Examine the design compilation results like resource utilization and timing result.
- Close your design example project.