GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/15/2025
Public
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A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
1.2.5. GTS Reset Sequencer Intel® FPGA IP
The GTS Reset Sequencer Intel® FPGA IP must be instantiated for each device side that uses transceivers. Based on your design, you must instantiate one or two instances of the IP:
- One GTS Reset Sequencer Intel® FPGA IP instance if your design uses transceivers on one side of the device.
- Two GTS Reset Sequencer Intel® FPGA IP instances if your design uses transceivers on both sides of the device.
For more information, refer to the Implementing the GTS Reset Sequencer Intel® FPGA IP section in the GTS Transceiver PHY User Guide.