GTS AXI Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
ID
817713
Date
5/15/2025
Public
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A.1.1. ebfm_barwr Procedure
A.1.2. ebfm_barwr_imm Procedure
A.1.3. ebfm_barrd_wait Procedure
A.1.4. ebfm_barrd_nowt Procedure
A.1.5. ebfm_cfgwr_imm_wait Procedure
A.1.6. ebfm_cfgwr_imm_nowt Procedure
A.1.7. ebfm_cfgrd_wait Procedure
A.1.8. ebfm_cfgrd_nowt Procedure
A.1.9. BFM Configuration Procedures
A.1.10. BFM Shared Memory Access Procedures
A.1.11. BFM Log and Message Procedures
A.1.12. Verilog HDL Formatting Functions
2.4.2.2. Configuration Space Bus and Device Numbering
Enumeration assigns the Root Port interface device number 0 on internal bus number 0. The ebfm_cfg_rp_ep procedure assigns the Endpoint to any device number on any bus number (greater than 0). The specified bus number is the secondary bus in the Root Port Configuration Space.