1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C IP
6. GTS JESD204C IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the GTS JESD204C IP User Guide
4.1. Installing and Licensing IP Cores
4.2. Altera® FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. GTS JESD204C IP Component Files
4.5. Creating a New Quartus® Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the GTS JESD204C IP Design
4.8. Programming an FPGA Device
5.1. Configuring the GTS Reset Sequencer IP
5.2. Reset Initialization
5.3. Configuration Phase
5.4. Link Reinitialization
5.5. SYSREF Sampling
5.6. Interrupt and Error Handling
5.7. Multi-Device Synchronization
5.8. Deterministic Latency
5.9. Pin Assignments
5.10. Dual Simplex Support
5.11. Analog Parameter Settings
5.12. Transceiver Toolkit
5.7.1. Multi-Device DAC Application for Subclass 1
SYSREF is the reference timing that start the LEMC counters in both converter devices and FPGA. You must determine the common E parameters for converter devices and logic devices, which is greater than the propagation time from TX to RX.
Figure 11. Multi-Device DAC Synchronization