GTS JESD204C IP User Guide

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ID 813959
Date 12/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C IP User Guide 2. Overview of the GTS JESD204C IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C IP 6. GTS JESD204C IP Parameters 7. Interface Signals 8. Control and Status Registers 9. Document Revision History for the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing IP Cores 4.2. Altera® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C IP x
5.1. Configuring the GTS Reset Sequencer IP 5.2. HVIO PLL Clocking Mode 5.3. Reset Initialization 5.4. Data Mapping Operation 5.5. Configuration Phase 5.6. Link Reinitialization 5.7. SYSREF Sampling 5.8. Interrupt and Error Handling 5.9. Multi-Device Synchronization 5.10. Deterministic Latency 5.11. Pin Assignments 5.12. Dual Simplex Support 5.13. Analog Parameter Settings 5.14. Transceiver Toolkit
5.3. Reset Initialization x
5.3.1. GTS JESD204C TX Reset Sequence 5.3.2. GTS JESD204C RX Reset Sequence
5.8. Interrupt and Error Handling x
5.8.1. Interrupt Configuration for TX and RX 5.8.2. Interrupt Top Half ISR Handler 5.8.3. Interrupt Bottom Half ISR Handler
5.9. Multi-Device Synchronization x
5.9.1. Multi-Device DAC Application for Subclass 1 5.9.2. Multi-Device ADC Application for Subclass 1
5.10. Deterministic Latency x
5.10.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C IP
6. GTS JESD204C IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the GTS JESD204C IP User Guide

6. GTS JESD204C IP Parameters

Table 18.   GTS JESD204C IP Parameters
Parameter Value Description
Main Tab
Device family Agilex™ 5 Supports Agilex™ 5 devices.
JESD204C wrapper
  • Base only
  • PHY only
  • Both Base and PHY
 Supports the JESD204C wrapper.
  • Base Only—generates the data link layer and transport layer.
  • PHY Only—generates the transceiver PHY layer only (hard PCS).
  • Both Base and PHY—generates both the base (data link layer and transport layer) and the transceiver PHY layer (hard PMA).
Data path
  • Receiver
  • Transmitter
  • Duplex
 Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic.
  • Receiver—instantiates the receiver to interface to the ADC.
  • Transmitter—instantiates the transmitter to interface to the DAC.
  • Duplex—instantiates the receiver and transmitter to interface to both the ADC and DAC.
JESD204C Subclass
  • 0
  • 1
 Select the GTS JESD204C subclass modes.
  • 0—Set subclass 0
  • 1—Set subclass 1
Data rate 5.0–28.1 Gbps Set the lane rate for each lane. The maximum rate is 28.1 Gbps. Refer to Performance and Resource Utilization for more information.
Datapath clocking mode PMA, System PLL

Specifies whether the transceiver's parallel clock or System PLL is used to clock data-path (Core/PMA Interface FIFOs).

For dual-simplex applications, use System PLL clocking. For non-dual-simplex applications, PMA clocking is recommended, but System PLL may be used if resource utilization is not a concern.
System/HVIO PLL frequency Variable
Specifies the System/HVIO PLL clock frequency used in the tile.
Note: The System/HVIO PLL is outside of the JESD204C IP. Use this option to set the System/HVIO PLL clock frequencies in the generated SDC constraint file. This setting does not directly affect the frequency of the System/HVIO PLL.
Enable HVIO PLL On, Off This options enables HVIO PLL as the alternative of System PLL.
HVIO PLL reference clock frequency Variable Sets the reference clock frequency for HVIO clock.
PLL/CDR reference clock frequency Variable Set the transceiver reference clock frequency for PLL and CDR/PLL or CDR. The frequency range available for you to choose depends on the data rate.
Enable PMA Avalon® memory-mapped interface On, Off Enables the Avalon® memory-mapped interface to access PMA registers
Enable debug endpoint for PMA Avalon® memory-mapped interface On, Off This option enables the Transceiver Native PHY IP core to include an embedded Native PHY debug master endpoint. This endpoint connects internally to the Avalon® memory-mapped interface slave interface of the Transceiver Native PHY and can access the reconfiguration space of the transceiver. It can perform certain test and debug functions through JTAG using System Console.
Enable PHY soft CSR On, Off This option enables soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug.
Enable Clkrx recovery logic On, Off

This option enables Clkrx refclk recovery related logic and ports (o_refclk_status_bus_out, i_refclk_cmd_bus_in). These ports would need to be connected to the GTS Reset Sequencer FPGA IP.

The REFCLK protection feature helps safeguard the clock input buffers. The system automatically monitors all input REFCLKs, and if any clock signal is lost, it will safely disable the affected buffer to prevent possible damage from a floating input.

To use this feature, enable the Enable Clkrx recovery logic option in the IP Parameter Editor when generating the IP. This setting only needs to be enabled once per GTS Reset Sequencer FPGA IP.
Note: For more information on connecting the newly added ports, refer to the GTS Transceiver PHY User Guide.
JESD204C Configurations Tab

Lanes per converter device (L)

 1, 2, 4, 6, 8 Set the number of lanes per converter device.

Converters per device (M)

 1–64 Set the number of converters per converter device.

Octets per frame (F)

 1–256 The number of octets per frame is derived from F= M*N'*S/(8*L).

Converter resolution (N)

 1–32 Set the number of conversion bits per converter.

Transmitted bits per sample (N')

 4–32 Set the number of transmitted bits per sample (JESD204 word size, which is in nibble group).
Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥ N + CS). Otherwise, parameter N' must be larger than or equal to parameter N (N'≥N).

Samples per converter per frame (S)

 1–32 Set the number of transmitted samples per converter per frame.

Multiblocks in an extended multiblock (E)

 1–32 Set the number of multiblock within an extended multiblock.

Control bits (CS)

 0–3 Set the number of control bits per conversion sample.

Control words (CF)

 0–31 Set the number of control words per frame clock period per link.

High-density user data format (HD)
  • 0
  • 1
 Turn on this option to set the data format. This parameter controls whether a sample may be divided over more lanes.
  • 1 (On)—High Density format
  • 0 (Off)—Data should not cross the lane boundary
Sync header configuration (SH_CONFIG)
  • CRC-12
  • Standalone command channel
 Set the sync header (SH) encoding configuration.
  • CRC-12—For the sync word to contain error detection information.
  • Standalone command channel—For the sync word to contain transmit commands and status information.
Frame clock frequency multiplier (FCLK_MULP)
  • 1
  • 2
 Select the frame clock frequency multiplier (FCLK). The default and recommended value is 1.
  • 1—Frame clock and link clock are at the same frequency.
  • 2—Frame clock frequency is two times the link clock frequency.
Frame data width multiplier (WIDTH_MULP) 1, 2, 4, 8 Select the data width multiplier between the application layer and transport layer.
Note: The multiplier value is auto-calculated based on the M, N, S, and F configurations. Select the smallest data width multiplier value on the list. Other data width multiplier values are not allowed.
Enable fabric to tile TX data pipestage (Transmitter)
  • Off
  • On
 Enable pipeline stage in TX datapath to tile for timing improvement. Turning on requires additional resources.
  • Off—Do not insert any pipeline stage. Minimum latency.
  • On—Insert 1 pipeline stage.
Note: For high data rates, Altera recommends that you enable pipeline stages for better timing.
TX LEMC offset (Transmitter) 0–255 TX LEMC offset from SYSREF. The default value is 0.
EMB error threshold (Receiver) 1–8 EMB error threshold to unlock EMB FSM back to initialization state. The default value is 8.
SH error threshold (Receiver) 1–16 Sync header error threshold to unlock SH FSM back to initialization state. The default value is 16.
RX LEMC offset (Receiver) 0–255 RX LEMC offset from SYSREF. The default value is 0.
RBD offset (Receiver) 0–1023 Elastic buffer release point (reference to LEMC) for Subclass 1 usage. The default value is 0.

One full LEMC, N number means (LEMC – N) cycles to release data in elastic buffer when deskew alignment is achieved.
Enable ECC in M20K DCFIFO (Receiver) On, Off Turn on to enable ECC feature if M20K is used as FIFO.
Lane polarity attribute (Receiver)
  • Optimize away
  • Writable
 Select whether you want the lane polarity attribute to be read-only (RO) or read and write (RW).
  • Optimize away—Select this option to enable the attribute to be read-only.
  • Writable—Select this option to enable the attribute to be read and write.

Applies only for RX.
Enable lane polarity detection (Receiver) 8'h0–8'hFFFF Specify the bit representing the polarity enable status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 7, and so on.

This value depends on the number of lanes you specify.
Polarity inversion (Receiver) 8'h0–8'hFFFF Specify the bit representing the polarity inversion status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 7, and so on.

This value depends on the number of lanes you specify.
Single lane mode (Receiver) On, Off Turn on only when you set the Sync header configuration parameter to Standalone command channel.
Multilink mode (Receiver) On, Off

Turn on this parameter when you want to implement synchronization between multiple GTS JESD204C RX IP instances. When you turn on this parameter, the j204c_rx_dev_emblock_align and j204c_rx_alldev_emblock_align signals are present.

The IP uses the j204c_rx_dev_emblock_align and j204c_rx_alldev_emblock_align signals together with the j204c_rx_dev_lane_align and j204c_rx_alldev_lane_align signals to achieve multi-device synchronization.

Refer to Receiver Signals for more information about these signals.
Configurations and Status Registers Tab

Enable CSR optimization

 On, Off

Turn on to optimize the usage of the registers, including the Avalon® memory-mapped interfaces.
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