GTS JESD204C IP User Guide

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ID 813959
Date 12/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C IP User Guide 2. Overview of the GTS JESD204C IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C IP 6. GTS JESD204C IP Parameters 7. Interface Signals 8. Control and Status Registers 9. Document Revision History for the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing IP Cores 4.2. Altera® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C IP x
5.1. Configuring the GTS Reset Sequencer IP 5.2. HVIO PLL Clocking Mode 5.3. Reset Initialization 5.4. Data Mapping Operation 5.5. Configuration Phase 5.6. Link Reinitialization 5.7. SYSREF Sampling 5.8. Interrupt and Error Handling 5.9. Multi-Device Synchronization 5.10. Deterministic Latency 5.11. Pin Assignments 5.12. Dual Simplex Support 5.13. Analog Parameter Settings 5.14. Transceiver Toolkit
5.3. Reset Initialization x
5.3.1. GTS JESD204C TX Reset Sequence 5.3.2. GTS JESD204C RX Reset Sequence
5.8. Interrupt and Error Handling x
5.8.1. Interrupt Configuration for TX and RX 5.8.2. Interrupt Top Half ISR Handler 5.8.3. Interrupt Bottom Half ISR Handler
5.9. Multi-Device Synchronization x
5.9.1. Multi-Device DAC Application for Subclass 1 5.9.2. Multi-Device ADC Application for Subclass 1
5.10. Deterministic Latency x
5.10.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C IP
6. GTS JESD204C IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the GTS JESD204C IP User Guide

5.2. HVIO PLL Clocking Mode

When configuring a GTS transceiver bank to support both PCIe* and non-PCIe* protocols that require a system PLL, a total of two system PLLs are needed. Because each GTS transceiver bank includes only one system PLL, the additional system PLL must be sourced from a neighboring GTS transceiver bank. For devices that contain only a single transceiver bank, refer to the I/O PLL in HVIO Bank as System PLL in the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs for additional information.

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