GTS JESD204C IP User Guide

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ID 813959
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C IP User Guide 2. Overview of the GTS JESD204C IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C IP 6. GTS JESD204C IP Parameters 7. Interface Signals 8. Control and Status Registers 9. Document Revision History for the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing IP Cores 4.2. Altera® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C IP x
5.1. Configuring the GTS Reset Sequencer IP 5.2. Reset Initialization 5.3. Configuration Phase 5.4. Link Reinitialization 5.5. SYSREF Sampling 5.6. Interrupt and Error Handling 5.7. Multi-Device Synchronization 5.8. Deterministic Latency 5.9. Pin Assignments 5.10. Dual Simplex Support 5.11. Analog Parameter Settings 5.12. Transceiver Toolkit
5.2. Reset Initialization x
5.2.1. GTS JESD204C TX Reset Sequence 5.2.2. GTS JESD204C RX Reset Sequence
5.6. Interrupt and Error Handling x
5.6.1. Interrupt Configuration for TX and RX 5.6.2. Interrupt Top Half ISR Handler 5.6.3. Interrupt Bottom Half ISR Handler
5.7. Multi-Device Synchronization x
5.7.1. Multi-Device DAC Application for Subclass 1 5.7.2. Multi-Device ADC Application for Subclass 1
5.8. Deterministic Latency x
5.8.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C IP
6. GTS JESD204C IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the GTS JESD204C IP User Guide

2.4. Performance and Resource Utilization

Table 7.   GTS JESD204C IP Performance
Device Family PMA Speed Grade Core Speed Grade Maximum Data Rate (Gbps)
FCLK_MULP = 1 FCLK_MULP = 2
Agilex™ 5 E-Series (Device Group B) 0 –4 17.16 15.5
–5 17.16 14.3
–6 17.16 11.9
Agilex™ 5 E-Series (Device Group A)/D-Series 0 –1 28.1 18.15
–2 28.1 18.15
–3 28.1 18.15

The following table lists the estimated resource utilization data of the GTS JESD204C IP. These results are obtained using the Quartus® Prime software targeting the Agilex™ 5 device.

The variations for resource utilization are configured with the following parameter settings:

Table 8.  Parameter Settings to Obtain the Resource Utilization Data
Parameter Setting
JESD204C Wrapper Both Base and PHY
JESD204C Subclass 1
Data Rate 17.16 Gbps
Reference Clock Frequency 260 MHz
Enable Scrambler (SCR) On
Enable Error Code Correction (ECC_EN) Off
Table 9.   GTS JESD204C IP Resource Utilization for Agilex™ 5 Devices
Variants L M F FCLK_MULP WIDTH_MULP ALM ALUT Logic Register M20K
TX 4 8 6 1 4 2348 2792 3018 8
4 8 6 2 2 2592 3157 3436 8
4 8 4 1 2 2226 2704 2558 8
4 8 4 2 1 2718 3277 3560 8
RX 2 8 12 1 2 2015 2925 2773 12
2 8 12 2 1 1833 2781 2489 12
1 2 8 1 1 932 1403 1152 5
1 2 8 2 1 940 1414 1156 5
1 4 24 1 1 1242 1537 1441 6
1 4 24 2 1 1068 1539 1445 6
3 2 4 1 2 2336 3441 2652 12
3 2 4 2 1 2356 3493 2910 12
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