1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C IP
6. GTS JESD204C IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the GTS JESD204C IP User Guide
4.1. Installing and Licensing IP Cores
4.2. Altera® FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. GTS JESD204C IP Component Files
4.5. Creating a New Quartus® Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the GTS JESD204C IP Design
4.8. Programming an FPGA Device
5.1. Configuring the GTS Reset Sequencer IP
5.2. Reset Initialization
5.3. Configuration Phase
5.4. Link Reinitialization
5.5. SYSREF Sampling
5.6. Interrupt and Error Handling
5.7. Multi-Device Synchronization
5.8. Deterministic Latency
5.9. Pin Assignments
5.10. Dual Simplex Support
5.11. Analog Parameter Settings
5.12. Transceiver Toolkit
5.4. Link Reinitialization
The GTS JESD204C IP implements a simple synchronous clear to all data and control logics during link reinitialization.
Link reinitialization occurs in two ways:
- You manually trigger link reinitialization by setting the link_reinit bit. The hardware clears the link_reinit and reinit_in_prog bits when link reinitialization completes.
- The hardware automatically triggers link reinitialization because of errors. You have full control, through the tx_err and rx_err registers, to set the specific type of errors to trigger link reinitialization automatically. The hardware clears the reinit_in_prog bit when link reinitialization completes.
Note: Avoid manually triggering link reinitialization (writing to 0x54) while link reinitialization is still in progress.
Note: Link reinitialization does not initiate SYSREF re-detection. Use the sysref_singledet bit to re-detect SYSREF edge. Link reinitialization affects only the transport layer and link layer; the CSR, transceiver, and the PHY-related logics are not affected.