8.2. Receiver Registers

Table 33. Address Table for JESD204C RX Registers
Address	Title
0x0	Link Lane Control Common
0x4	Link Lane Control 0
0x8	Link Lane Control 1
0xC	Link Lane Control 2
0x10	Link Lane Control 3
0x14	Link Lane Control 4
0x18	Link Lane Control 5
0x1C	Link Lane Control 6
0x20	Link Lane Control 7
0x50	Transport Layer Control
0x54	SYSREF Control
0x60	JESD204 RX Error
0x64	JESD204 RX Error Interrupt Enable
0x68	JESD204 RX Error Link Reinit Enable
0x80	JESD204 RX Status 0
0x8C	JESD204 RX Status 3
0x90	JESD204 RX Status 4
0x94	JESD204 RX Status 5
0x98	JESD204 RX Status 6
0x9C	JESD204 RX Status 7
0xC0	JESD204 RX Converter Parameter 1
0xC4	JESD204 RX Converter Parameter 2

Table 34. lane_ctrl_common
Common lane control and assignment. The common lane control applies to all lanes in the link.

Offset: 0x0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit	Name	Description	Attribute	Reset
11	rx_gb_lben	Enable 64bit interface loopback from TX. Instead of taking RX data from XCVR, TX loopback data is muxed in for subsequent RX operation. This mode is not valid for configuration that does not include 66/64 Gearbox.	RW	0x0
9:6	rx_thresh_sh_err	The number of consecutive erroneous sequences required to force the algorithm back to itnitial SH_INIT. 0-based value. 0=threshold of 1. ‘d15= threshold of 16.	RW	compile-time specific
5:3	rx_thresh_emb_err	The number of consecutive erroneous sequences required to force the algorithm back to itnitial EMB_INIT. 0-based value. 0=threshold of 1. ‘d7= threshold of 8.	RW	compile-time specific
0	bit_reversal	This is a compile-time option which needs to be set before IP generation. 0 = LSB-first serialization. 1 = MSB-first serialization. Note: JESD204C converter device may support either MSB-first serialization or LSB-first serialization. When bit_reversal = 1, the word aligner reverses RX parallel data bits upon receiving the PMA deserialised data. For example; in 64-bit mode => D[63:0] is rewired to D[0:63]	RO	0x0

Table 35. lane_ctrl_0
Lane control and assignment for Lane 0.

Offset: 0x4
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 36. lane_ctrl_1
Lane control and assignment for Lane 1.

Offset: 0x8
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 37. lane_ctrl_2
Lane control and assignment for Lane 2.

Offset: 0xC
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 38. lane_ctrl_3
Lane control and assignment for Lane 3.

Offset: 0x10
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 39. lane_ctrl_4
Lane control and assignment for Lane 4.

Offset: 0x14
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 40. lane_ctrl_5
Lane control and assignment for Lane 5.

Offset: 0x18
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 41. lane_ctrl_6
Lane control and assignment for Lane 6.

Offset: 0x1C
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 42. lane_ctrl_7
Lane control and assignment for Lane 7.

Offset: 0x20
Bit	Name	Description	Attribute	Reset
0	lane_polarity_en	Set 1 to to enable Lane Polarity detection. When set, the RX interface detects and inverts the polarity of the RX data. If CSR_OPT=1 or POL_EN_ATTR = 0, this is register is RO. Else it’s RW.	RW/RO	POL_EN[x]

Table 43. tl_ctrl
Transport layer control.

Offset: 0x50
Bit	Name	Description	Attribute	Reset
3	tl_en	Transport Layer enabled. This will be always 1 for GTS	RO	compile-time specific
2:1	width_mult	This is a compile-time option which needs to be set before IP generation. Total Sample width multiplier 2’b00: Width equals to MNS 2’b01: Width equals to 2MNS 2’b10: Width equals to 4MNS 2’b11: Width equals to 8MN*S	RO	compile-time specific
0	fclk_mult	This is a compile-time option which needs to be set before IP generation. Frame Clock Multiplier 0: Frame Clock Freq is the same as Link Clock Freq. 1: Frame Clock Freq is 2x of Link Clock Freq.	RO	compile-time specific

Table 44. sysref_ctrl
SYSREF control.

Offset: 0x54

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit	Name	Description	Attribute	Reset
26	force_rbd_release	Setting this bit will force RBD elastic buffer to be released immediately when the latest arrival lane arrived in the system. It indirectly forces rbd_offset == rx_status0 (0x80) rbd_count. This register overrides rbd_offset.	RW	compile-time specific
25:16	rbd_offset	RX Buffer Delay (RBD) offset. RX elastic buffer will align the data from multiple lanes of the link and release the buffer at the LEMC boundary (rbd_offset = 0). This register provides flexibility for an early RBD release opportunity. Legal value of RBD offset is from (E16-1) or (E32-1) down to 0 as it is aligned in number of link clocks. If rbd_offset is set out of the legal value, the RBD elastic buffer will be immediately released. (E16) refers to 128bit design. (E32) refers to 64bit design.	RW	compile-time specific
15:8	lemc_offset	Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LEMC counter will be reset to the value set in lemc_offset. LEMC counter operates in link clock domain therefore the legal value for the counter is from 0 to (Ex32)-1. In the event that (Ex32)-1 > 255, the design has no capability to adjust the LEMC for offset greater than 255. If (Ex32)-1 < 255, and an out-of-range value is set, the LEMC offset will be internally reset to 0. Note: By default, the rising edge of SYSREF will reset the LEMC counter to 0. However, if the system design has large phase offset between the SYSREF sampled by the converter device and the FPGA, user can virtually shift the SYSREF edges by changing the LEMC offset reset value using this register.	RW	compile-time specific
2	sysref_singledet	This register enables LEMC realignment with a single sample of rising edge of SYSREF. The bit is autocleared by hardware once SYSREF is sampled. If the user requires SYSREF to be sampled again (due to link reset or reinitialization), user must set this bit again. This register also has another critical function: JESD204C IP core will never send EoEMB unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled at TX (logic device) and the deterministic timing of EoEMB transmission. 0 = Any rising edge of SYSREF will not reset the LEMC counter. 1 = Resets the LEMC counter on the first rising edge of SYSREF and then clears this bit. (Default) Note: It is highly recommended to use sysref_singledet with sysref_alwayson even if user wants to do SYSREF continuous detection mode. This is because this register is able to indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period. If CSR_OPT=1, this bit will not be able to be cleared by hardware hence LEMC counter will be always reset to new SYSREF edge.	RW1S	0x1
1	sysref_alwayson	This register enables LEMC realignment at every rising edge of SYSREF. LEMC counter is reset when every SYSREF transition from 0 to 1 is detected. 0 = Any rising edge of SYSREF will not reset the LEMC counter. 1 = Continuously resets LEMC counter at every SYSREF rising edge. Note: When this bit is set, the SYSREF period will be checked that it never violates internal extended multiblock period and this period can only be n-integer multiplied of (Ex32). If the SYSREF period is different from the local extended multiblock period, register rx_err (0x60) sysref_lemc_err will be asserted and an interrupt will be triggered. If user wants to change SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF.	RW	0x0
0	link_reinit	JESD204C IP core will reinitialize the RX link by resetting all internal pipestages and status, but not including SYSREF detection information. (This bit will automatically be cleared once link reinitialization is entered by hardware). 0 = No link reinit request (Default) 1 = Reinitialize the link.	RW1S	0x0

Table 45. rx_err
This register logs errors detected in the FPGA IP. Each set bit in the register will generate interrupt, if enabled by corresponding bits in the RX Error Enable register (rx_err_enable (0x64)). After servicing the interrupt, software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending.

Offset: 0x60
Bit	Name	Description	Attribute	Reset
22	ecc_fatal_err	Assert when ECC fatal error occurs. This reflects a double bit error detected and uncorrected.	RW1C	0x0
21	ecc_corrected_err	Assert when ECC error has been corrected. This reflects a single bit error detected and corrected.	RW1C	0x0
20	eb_full_err	Assert when any of the RX elastic buffer detected an overflow condition.	RW1C	0x0
19	emb_unlock_err	Assert when any of the EMB alignment logic detected an “unlock” due to error count >= error threshold. I.e EMB_LOCK= 1à0.	RW1C	0x0
18	sh_unlock_err	Assert when any of Sync Header alignment logic detected an “unlock” due to error count >= error threshold. I.e SH_LOCK= 1à0.	RW1C	0x0
17	rx_gb_ovnerflow_err	Assert when overflow happens on any of the lane’s RX gearbox.	RW1C	0x0
16	rx_gb_underflow_err	Assert when underflow happens on any of the lane’s RX gearbox.	RW1C	0x0
14	crc_err	The Rx CRC generator has calculated a parity which does not match the parity received in the sync word	RW1C	0x0
11	cmd_par_err	The final parity bit in the command channel data for a given sync word does not match the calculated parity for the received command channel bits.	RW1C	0x0
10	invalid_eoemb	The EoEMB identifier in the pilot signal has an unexpected value.	RW1C	0x0
9	invalid_eomb	The “00001” sequence in the pilot signal is not received at an expected location in the sync word	RW1C	0x0
8	invalid_sync_header	“11” or “00” received in expected sync header location	RW1C	0x0
7	lane_deskew_err	Asserted when lane to lane deskew exceed the LEMC boundary. This error will trigger when rbd_offset is not correctly programmed or the lane to lane skew within the device or across multi-device has exceeded the LEMC boundary. EoEMB for all lanes should within one LEMC boundary. User should refer to the application note on deterministic latency for more information.	RW1C	0x0
4	cdr_locked_err	Detected 1 or more lanes of CDR locked loose lock when JESD204C link is running.	RW1C	0x0
3	cmd_ready_err	This error bit is applicable only if Command Channel is used in JESD204C link. This error bit will be asserted if the upstream component de-assert j204c_rx_cmd_ready signal while Link Layer is sending command (via j204c_rx_cmd_valid).	RW1C	0x0
2	frame_data_ready_err	This error bit will be asserted if the RX detects data ready by the upstream component is 0 on the AV-ST bus when data is valid. The Transport Layer expects the upstream device in the system (AV-ST sink component) will always be ready to receive the valid data from the Transport Layer. Note: If this error detection is not required, the user can tie off the data ready signal from the upstream to 1, j204_rx_avst_ready in Transport Layer. This error will only assert if TL is instantiated.	RW1C	0x0
1	dll_data_ready_err	This error bit will be asserted if the RX detects data ready by the upstream component is 0 on the AV-ST bus when data is valid. By design, the JESD204C RX IP core expects the upstream device (JESD204C Transport Layer/Application Layer) will always be ready to receive the valid data from JESD204C RX IP core. Note: If this error detection is not required, the user can tie off the AV-ST signal j204_rx_avst_ready to 1.	RW1C	0x0
0	sysref_lemc_err	When register sysref_ctrl (0x54) sysref_alwayson is set to 1, the LEMC counter will check whether SYSREF period matches the LEMC counter where it is n-integer multiplier of the (Ex32). If SYSREF period does not match the LEMC period, this bit will be asserted.	RW1C	0x0

Table 46. rx_err_en
This register enables the error types that will generate interrupt. Setting 0 to the register bits will disable the specific error type from generating interrupt.

Offset: 0x64
Bit	Name	Description	Attribute	Reset
22	ecc_fatal_err_en	ECC fatal error interrupt enable	RW	0x1
21	ecc_corrected_err_en	ECC corrected error interrupt enable	RW	0x0
20	eb_full_err_en	Elastic buffer full error interrupt enable	RW	0x1
19	emb_unlock_err_en	EMB alignment unlock error interrupt enable	RW	0x1
18	sh_unlock_err_en	Sync Header alignment unlock error interrupt enable	RW	0x1
17	rx_gb_overflow_err_en	Gearbox overflow error interrupt enable	RW	0x1
16	rx_gb_underflow_err_en	Gearbox underflow error interrupt enable	RW	0x1
14	crc_err_en	CRC error interrupt enable	RW	0x1
11	cmd_par_err_en	Command Parity error interrupt enable	RW	0x1
10	invalid_eoemb_en	Invalid EoEMB error interrupt enable	RW	0x1
9	invalid_eomb_en	Invalid EoMB error interrupt enable	RW	0x1
8	invalid_sync_header_en	Invalid Sync Header error interrupt enable	RW	0x1
7	lane_deskew_err_en	Lane Deskew error interrupt enable	RW	0x1
4	cdr_locked_err_en	CDR lost lock error interrupt enable	RW	0x1
3	cmd_ready_err_en	Command data ready error interrupt enable	RW	0x0
2	frame_data_ready_err_en	Frame data ready error interrupt enable	RW	0x0
1	dll_data_ready_err_en	Link data ready error interrupt enable	RW	0x0
0	sysref_lemc_err_en	SYSREF LEMC error interrupt enable	RW	0x1

Table 47. rx_err_link_reinit
This register enables the error types that will generate link reinitialization. Setting 0 to the register bits will disable the specific error type from link reinitialization.

Offset: 0x68
Bit	Name	Description	Attribute	Reset
22	ecc_fatal_err_en_reinit	ECC fatal error reinit enable	RW	0x0
21	ecc_corrected_err_en_reinit	ECC corrected error reinit enable	RW	0x0
20	eb_full_err_en_reinit	Elastic buffer full error reinit enable	RW	0x0
14	crc_err_en_reinit	CRC error reinit enable	RW	0x0
11	cmd_par_err_en_reinit	Command Parity error reinit enable	RW	0x0
10	invalid_eoemb_en_reinit	Invalid EoEMB error reinit enable	RW	0x0
9	invalid_eomb_en_reinit	Invalid EoMB error reinit enable	RW	0x0
8	invalid_sync_header_en_reinit	Invalid Sync Header error reinit enable	RW	0x0
7	lane_deskew_err_en_reinit	Lane Deskew error reinit enable	RW	0x0
3	cmd_ready_err_en_reinit	Command data ready error reinit enable	RW	0x0
2	frame_data_ready_err_en_reinit	Frame data ready error reinit enable	RW	0x0
1	dll_data_ready_err_en_reinit	Link data ready error reinit enable	RW	0x0
0	sysref_lemc_err_en_reinit	SYSREF LEMC error reinit enable	RW	0x0

Table 48. rx_status0
Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x80

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit	Name	Description	Attribute	Reset
24	src_reset_in_prog	Indicate rx_ready	ROV	0x1
23	sysref_det_pending	Indicate that sysref is yet to be detected. sysref_ctrl.sysref_singledet needs to be set to enable Link initialization.	ROV	0x0
22	reinit_in_prog	Indicates that auto or manual link reinit is in progress.	ROV	0x0
21:12	rbd_count_early	When rbd_count_early = 0, this indicates that the earliest lane arrives within the link at the LEMC boundary. When rbd_count_early = 1, this indicates that the earlist lane arrives within the link at 1 link clock cycle after the LEMC boundary.	ROV	0x0
11:2	rbd_count	Legal value reported from this register is 0 to 511 for 128-bit design or 1023 for 64-bit design. When rbd_count = 0, this indicates that the latest lane arrives within the link at the LEMC boundary. When rbd_count = 1, this indicates that the latest lane arrives within the link at 1 link clock cycle after the LEMC boundary. Note: When the latest lane arrival in the link is too close to the LEMC boundary, it is recommended to set the RBD release opportunity (register sysref_ctrl 0x54 rbd_offset) at least 2 link clocks away from the rbd_count to accommodate for worse case power cycle variation. User should refer to the application note on deterministic latency for more information.	ROV	0x0
1:0	sh_config	b00: CRC-12 b01: Standalone command channel b10: Reserved (CRC-3) b11: Reserved	RO	compile-time specific

Table 49. rx_status3
Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x8C
Bit	Name	Description	Attribute	Reset
7	lane7_rx_cdr_locked	RX CDR lock status flag for Lane7	ROV	0x0
6	lane6_rx_cdr_locked	RX CDR lock status flag for Lane6	ROV	0x0
5	lane5_rx_cdr_locked	RX CDR lock status flag for Lane5	ROV	0x0
4	lane4_rx_cdr_locked	RX CDR lock status flag for Lane4	ROV	0x0
3	lane3_rx_cdr_locked	RX CDR lock status flag for Lane3	ROV	0x0
2	lane2_rx_cdr_locked	RX CDR lock status flag for Lane2	ROV	0x0
1	lane1_rx_cdr_locked	RX CDR lock status flag for Lane1	ROV	0x0
0	lane0_rx_cdr_locked	RX CDR lock status flag for Lane0	ROV	0x0

Table 50. rx_status4
Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x90
Bit	Name	Description	Attribute	Reset
7	lane7_sh_lock	RX Sync Header alignment lock status flag for Lane7	ROV	0x0
6	lane6_sh_lock	RX Sync Header alignment lock status flag for Lane6	ROV	0x0
5	lane5_sh_lock	RX Sync Header alignment lock status flag for Lane5	ROV	0x0
4	lane4_sh_lock	RX Sync Header alignment lock status flag for Lane4	ROV	0x0
3	lane3_sh_lock	RX Sync Header alignment lock status flag for Lane3	ROV	0x0
2	lane2_sh_lock	RX Sync Header alignment lock status flag for Lane2	ROV	0x0
1	lane1_sh_lock	RX Sync Header alignment lock status flag for Lane1	ROV	0x0
0	lane0_sh_lock	RX Sync Header alignment lock status flag for Lane0	ROV	0x0

Table 51. rx_status5
Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x94
Bit	Name	Description	Attribute	Reset
7	lane7_emb_lock	RX EMB alignment lock status flag for Lane7	ROV	0x0
6	lane6_emb_lock	RX EMB alignment lock status flag for Lane6	ROV	0x0
5	lane5_emb_lock	RX EMB alignment lock status flag for Lane5	ROV	0x0
4	lane4_emb_lock	RX EMB alignment lock status flag for Lane4	ROV	0x0
3	lane3_emb_lock	RX EMB alignment lock status flag for Lane3	ROV	0x0
2	lane2_emb_lock	RX EMB alignment lock status flag for Lane2	ROV	0x0
1	lane1_emb_lock	RX EMB alignment lock status flag for Lane1	ROV	0x0
0	lane0_emb_lock	RX EMB alignment lock status flag for Lane0	ROV	0x0

Table 52. rx_status6
Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x98
Bit	Name	Description	Attribute	Reset
7	lane7_rx_eb_full	RX Elastic Buffer full status flag for Lane7	ROV	0x0
6	lane6_rx_eb_full	RX Elastic Buffer full status flag for Lane6	ROV	0x0
5	lane5_rx_eb_full	RX Elastic Buffer full status flag for Lane5	ROV	0x0
4	lane4_rx_eb_full	RX Elastic Buffer full status flag for Lane4	ROV	0x0
3	lane3_rx_eb_full	RX Elastic Buffer full status flag for Lane3	ROV	0x0
2	lane2_rx_eb_full	RX Elastic Buffer full status flag for Lane2	ROV	0x0
1	lane1_rx_eb_full	RX Elastic Buffer full status flag for Lane1	ROV	0x0
0	lane0_rx_eb_full	RX Elastic Buffer full status flag for Lane0	ROV	0x0

Table 53. rx_status7
Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x9C
Bit	Name	Description	Attribute	Reset
7	lane7_rx_polarity	RX Polarity Inversion status flag for Lane7	ROV	0x0
6	lane6_rx_polarity	RX Polarity Inversion status flag for Lane6	ROV	0x0
5	lane5_rx_polarity	RX Polarity Inversion status flag for Lane5	ROV	0x0
4	lane4_rx_polarity	RX Polarity Inversion status flag for Lane4	ROV	0x0
3	lane3_rx_polarity	RX Polarity Inversion status flag for Lane3	ROV	0x0
2	lane2_rx_polarity	RX Polarity Inversion status flag for Lane2	ROV	0x0
1	lane1_rx_polarity	RX Polarity Inversion status flag for Lane1	ROV	0x0
0	lane0_rx_polarity	RX Polarity Inversion status flag for Lane0	ROV	0x0

Table 54. rx_converter_param1
Link and transport control configuration per converter parameters.

Offset: 0xC0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit	Name	Description	Attribute	Reset
31:30	CS	Number of control bits per converter sample. 1-based value. I.e 0=0 bit, 1=1 bit.	RO	compile-time specific
29	HD	High Density format.	RO	compile-time specific
28:24	N	Number of data bits per converter sample. 0-based value. I.e 0=1 bit, 1=2 bits. Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific
23:16	M	Number of converter per device. 0-based value. I.e 0=1 converter, 1=2 converters. Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific
15:8	F	Number of octets per frame. 0-based value. I.e 0=1 octet, 1=2 octets. Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific
3:0	L	Number of lanes per link. 0-based value. I.e 0=1 lane, 1=2 lanes. Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific

Table 55. rx_converter_param2
Link and Transport control configuration per converter parameters.

Offset: 0xC4

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit	Name	Description	Attribute	Reset
31:24	E	Number of multiblock within an extended multiblock. 0-based value. I.e 0=1 multiblock to form extended mutiblock, 1=2 mutliblock to form an extended multiblock. If (256 Mod F) =1, E must be greater than 1. (Register value should be greater than 0) Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific
20:16	CF	Number of control words per frame clock per link. 1-based value. I.e 0=0 word, 1=1 word.	RO	compile-time specific
12:8	S	Number of samples per converter frame cycle. 0-based value. I.e 0=1 sample, 1=2 samples. Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific
7:5	subclass_ver	Device Subclass Version b000: Subclass 0 b001: Subclass 1	RO	compile-time specific
4:0	NP	Number of data bits+control bits+tail bits per converter sample. 0-based value. I.e 0=1 bit, 1=2 bits. Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.	RO	compile-time specific

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GTS JESD204C IP User Guide

8.2. Receiver Registers