GTS JESD204C IP User Guide

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ID 813959
Date 12/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS JESD204C IP User Guide 2. Overview of the GTS JESD204C IP 3. Functional Description 4. Getting Started 5. Designing with the GTS JESD204C IP 6. GTS JESD204C IP Parameters 7. Interface Signals 8. Control and Status Registers 9. Document Revision History for the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP x
2.1. Release Information 2.2. Device Family Support 2.3. GTS JESD204C IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. GTS Reset Sequencer IP Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing IP Cores 4.2. Altera® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. GTS JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the GTS JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the GTS JESD204C IP x
5.1. Configuring the GTS Reset Sequencer IP 5.2. HVIO PLL Clocking Mode 5.3. Reset Initialization 5.4. Data Mapping Operation 5.5. Configuration Phase 5.6. Link Reinitialization 5.7. SYSREF Sampling 5.8. Interrupt and Error Handling 5.9. Multi-Device Synchronization 5.10. Deterministic Latency 5.11. Pin Assignments 5.12. Dual Simplex Support 5.13. Analog Parameter Settings 5.14. Transceiver Toolkit
5.3. Reset Initialization x
5.3.1. GTS JESD204C TX Reset Sequence 5.3.2. GTS JESD204C RX Reset Sequence
5.8. Interrupt and Error Handling x
5.8.1. Interrupt Configuration for TX and RX 5.8.2. Interrupt Top Half ISR Handler 5.8.3. Interrupt Bottom Half ISR Handler
5.9. Multi-Device Synchronization x
5.9.1. Multi-Device DAC Application for Subclass 1 5.9.2. Multi-Device ADC Application for Subclass 1
5.10. Deterministic Latency x
5.10.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the GTS JESD204C IP User Guide
2. Overview of the GTS JESD204C IP
3. Functional Description
4. Getting Started
5. Designing with the GTS JESD204C IP
6. GTS JESD204C IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the GTS JESD204C IP User Guide

8.1. Transmitter Registers

Table 23.  Address Table for JESD204C TX Registers
Address Title
0x0 Link Lane Control (Common)
0x50 Transport Layer (TL) Control
0x54 SYSREF Control
0x60 JESD204 TX Error Status
0x64 JESD204 TX Error Interrupt Enable
0x68 JESD204 RX Error Link Reinit Enable
0x80 JESD204 TX Status 0
0xC0 JESD204 TX Converter Parameter 1
0xC4 JESD204 TX Converter Parameter 2
Note: When CSR_OPT=1, AVMM access to all CSR will be lost.
Table 24.  lane_ctrl_common

Common lane control and assignment. The common lane control applies to all lanes in the link.

Offset: 0x0

Note:  For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
3 sysclk_dis

This is a compile-time option which needs to be set before IP generation.

0: Operate in System clocking mode.

1: Operate in Native Clocking mode.

 RO compile-time specific
0 bit_reversal

This is a compile-time option which needs to be set before IP generation.

0 = LSB-first serialization.

1 = MSB-first serialization.

Note:

JESD204C converter device may support either MSB-first serialization or LSB-first serialization.

When bit_reversal = 1, the word aligner reverses TX parallel data bits before transmitting it to the PMA for serialization. For example; in 64-bit mode => D[63:0] is rewired to D[0:63]

 RO 0x0
Table 25.  tl_ctrl

Transport layer control.

Offset: 0x50
Bit Name Description Attribute Reset
3 tl_en

Transport Layer enabled.

This will be always 1 for GTS.

 RO compile-time specific
2:1 width_mult

This is a compile-time option which needs to be set before IP generation.

Total Sample width multiplier

2’b00: Width equals to M*N*S

2’b01: Width equals to 2*M*N*S

2’b10: Width equals to 4*M*N*S

2’b11: Width equals to 8*M*N*S

 RO compile-time specific
0 fclk_mult

This is a compile-time option which needs to be set before IP generation.

Frame Clock Multiplier

0: Frame Clock Freq is the same as Link Clock Freq.

1: Frame Clock Freq is 2x of Link Clock Freq.

 RO compile-time specific
Table 26.  sysref_ctrl

SYSREF control.

Offset: 0x54
Bit Name Description Attribute Reset
15:8 lemc_offset

Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LEMC counter will be reset to the value set in lemc_offset. LEMC counter operates in link clock domain therefore the legal value for the counter is from 0 to (Ex32)-1. In the event that (Ex32)-1> 255, the design has no capability to adjust the LEMC for offset greater than 255. If (Ex32)-1 < 255, and an out-of-range value is set, the LEMC offset will be internally reset to 0.

Note:

By default, the rising edge of SYSREF will reset the LEMC counter to 0. However, if the system design has large phase offset between the SYSREF sampled by the converter device and the FPGA, user can virtually shift the SYSREF edges by changing the LEMC offset reset value using this register.

 RW compile-time specific
2 sysref_singledet

This register enables LEMC realignment with a single sample of rising edge of SYSREF. The bit is autocleared by hardware once SYSREF is sampled. If the user requires SYSREF to be sampled again (due to link reset or reinitialization), user must set this bit again.

This register also has another critical function: JESD204C IP core will never send EoEMB unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled at RX (converter device) and the deterministic timing of EoEMB transmission.

0 = Any rising edge of SYSREF will not reset the LEMC counter.

1 = Resets the LEMC counter on the first rising edge of SYSREF and then clears this bit. (Default)

Note:

It is highly recommended to use sysref_singledet with sysref_alwayson even if user wants to do SYSREF continuous detection mode. This is because this register is able to indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period.

If CSR_OPT=1, this bit will not be able to be cleared by hardware hence LEMC counter will be always reset to new SYSREF edge.

 RW1S 0x1
1 sysref_alwayson

This register enables LEMC realignment at every rising edge of SYSREF. LEMC counter is reset when every SYSREF transition from 0 to 1 is detected.

0 = Any rising edge of SYSREF will not reset the LEMC counter.

1 = Continuously resets LEMC counter at every SYSREF rising edge.

Note: When this bit is set, the SYSREF period will be checked that it never violates internal extended multiblock period and this period can only be n-integer multiplied of (Ex32). If the SYSREF period is different from the local extended multiblock period, register tx_err (0x60) sysref_lemc_err will be asserted and an interrupt will be triggered. If user wants to change SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF.
RW 0x0
0 link_reinit

JESD204C IP core will reinitialize the TX link by resetting all internal pipestages and status, but not including SYSREF detection information.

(This bit will automatically be cleared once link reinitialization is entered by hardware).

0 = No link reinit request (Default)

1 = Reinitialize the link.

 RW1S 0x0
Table 27.  tx_err

This register logs errors detected in the FPGA IP. Each set bit in the register will generate an interrupt, if enabled by corresponding bits in the TX Error Enable register (tx_err_enable (0x64)). After servicing the interrupt, the software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending.

Offset: 0x60
Bit Name Description Attribute Reset
8 tx_gb_ overflow _err Assert when overflow happens on any of the lane’s TX gearbox. RW1C 0x0
7 tx_gb_underflow_err Assert when underflow happens on any of the lane’s TX gearbox. RW1C 0x0
4

txpll_lock_err

 Detected 1 or more lanes of ux_all_synthlockstatus (from Tile) drop when JESD204C link is running. This means XCVR PLL is unexpectedly unlocked. RW1C 0x0
3 cmd_invalid_err This error bit is applicable only if Command Channel is used in JESD204C link. This error bit will be asserted if the upstream component de-assert j204c_tx_cmd_valid signal while Link Layer is requesting for command (via j204c_tx_cmd_ready). RW1C 0x0
2 frame_data_invalid_err This error bit will be asserted if the upstream component de-asserts j204c_tx_avst_valid signal at the Transport Layer AV-ST bus. The Transport Layer expects the upstream device in the system will always send the valid data with zero latency when j204c_tx_avst_ready is asserted by the Transport Layer. RW1C 0x0
1 dll_data_invalid_err This error bit will be asserted if the Link Layer TX detects data invalid on the AV-ST bus when data is requested. By design, the JESD204C TX Link Layer expects the upstream device (JESD204C Transport Layer) will always send the valid data with zero latency when ready is asserted. RW1C 0x0
0 sysref_lemc_err When register sysref_ctrl (0x54) sysref_alwayson is set to 1, the LEMC counter will check whether SYSREF period matches the LEMC counter where it is n-integer multiplier of the (Ex32). If SYSREF period does not match the LEMC period, this bit will be asserted. RW1C 0x0
Note: When CSR_OPT=1, all error reporting via this CSR is lost.
Table 28.  tx_err_en

This register enables the error types that will generate interrupt. Setting 0 to the register bits will disable the specific error type from generating interrupt.

Offset: 0x64
Bit Name Description Attribute Reset
8 tx_gb_overflow_err_en TX Gearbox overflow error interrupt enable RW 0x1
7 tx_gb_underflow_err_en TX Gearbox underflow error interrupt enable RW 0x1
4 txpll_lock_err_en TX XCVR PLL Lock error interrupt enable RW 0x1
3 cmd_invalid_err_en Command invalid error interrupt enable RW 0x0
2 frame_data_invalid_err_en Frame data invalid error interrupt enable RW 0x0
1 dll_data_invalid_err_en Link data invalid error interrupt enable RW 0x0
0 sysref_lemc_err_en SYSREF LEMC error interrupt enable RW 0x1
Table 29.  tx_err_link_reinit

This register enables the error types that will generate link reinitialization. Setting 0 to the register bits will disable the specific error type from link reinitialization.

Offset: 0x68
Bit Name Description Attribute Reset
3 cmd_invalid_err_en_reinit Command invalid error reinit enable RW 0x0
2 frame_data_invalid_err_en_reinit Frame data invalid error reinit enable RW 0x0
1 dll_data_invalid_err_en_reinit Link data invalid error reinit enable RW 0x0
0 sysref_lemc_err_en_reinit SYSREF LEMC error reinit enable. RW 0x0
Note: When CSR_OPT=1, TX IP will not trigger any reinit due to the error stated in these registers as all the *en_reinit is defaulted to zero
Table 30.  tx_status0

Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x80
Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
4 src_reset_in_prog Indicate tx_ready ROV 0x1
3 sysref_det_pending Indicate that sysref is yet to be detected. sysref_ctrl.sysref_singledet needs to be set to enable Link initialization. ROV 0x0
2 reinit_in_prog Indicates that auto or manual link reinit is in progress. ROV 0x0
1:0 sh_config

Sync Header encoding configuration

b00: CRC-12

b01: Standalone command channel

b10: Reserved (CRC-3)

b11: Reserved (FEC)

 RO compile-time specific
Table 31.  tx_converter_param1

Link and transport control configuration per converter parameters.

Offset: 0xC0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:30 CS Number of control bits per converter sample. 1-based value. I.e 0=0 bit, 1=1 bit. RO compile-time specific
29 HD High Density format. RO compile-time specific
28:24 N

Number of data bits per converter sample. 0-based value. I.e 0=1 bit, 1=2 bits.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
23:16 M

Number of converters per device. 0-based value. I.e 0=1 converter, 1=2 converters.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
15:8 F

Number of octets per frame. 0-based value. I.e 0=1 octet, 1=2 octets.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
3:0 L

Number of lanes per link. 0-based value. I.e 0=1 lane, 1=2 lanes.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
Table 32.  tx_converter_param2

Link and transport control configuration per converter parameters.

Offset: 0xC4

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:24 E

Number of multiblock within an extended multiblock. 0-based value. I.e 0=1 multiblock to form extended mutiblock, 1=2 mutliblock to form an extended multiblock.

If (256 Mod F) =1, E must be greater than 1. (Register value should be greater than 0)

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
20:16 CF Number of control words per frame clock per link. 1-based value. I.e 0=0 word, 1=1 word. RO compile-time specific
12:8 S

Number of samples per converter frame cycle. 0-based value. I.e 0=1 sample, 1=2 samples.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
7:5 subclass_ver

Device Subclass Version

b000: Subclass 0

b001: Subclass 1

 RO compile-time specific
4:0 NP

Number of data bits+control bits+tail bits per converter sample. 0-based value. I.e 0=1 bit, 1=2 bits.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
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