Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series
ID
813955
Date
6/06/2025
Public
3.4.2.4. LPDDR5 Interfaces
The following table shows the maximum number of LPDDR5 interfaces per device.
Package | Number of HSIO Banks | HSIO Pins Count | Avalon® Streaming Interface x16 Support | LPDDR5 1x32/2x16 |
LPDDR5 1x16 |
---|---|---|---|---|---|
B15A | 1 | 62 | No | – | 1 |
Yes | – | – | |||
B23B B23A |
1 | 96 | No | 1 | 2 |
Yes | – | 1 | |||
M16A B23B B32A |
2 | 192 | No | 2 | 2 |
Yes | 1 | 2 | |||
B32A | 4 | 384 | No | 4 | 4 |
Yes | 3 | 4 |
Note: These values correspond to Fabric EMIF instances.