Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

Download PDF
ID 813955
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Migration Scope 3. Functional Area 4. Quartus® Prime Software Design Migration 5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series
2. Migration Scope x
2.1. Migration Supported Packages 2.2. Migration Scenarios 2.3. Considerations for Migration Planning
2.2. Migration Scenarios x
2.2.1. Vertical Migration 2.2.2. Conditional Migration
2.3. Considerations for Migration Planning x
2.3.1. Package B15A 2.3.2. Package M16A 2.3.3. Package B18A 2.3.4. Package B23B 2.3.5. Package B23A 2.3.6. Package B32A
3. Functional Area x
3.1. I/O 3.2. LVDS SERDES 3.3. Configuration 3.4. External Memory Interface 3.5. HPS 3.6. Transceiver 3.7. Power 3.8. Sensor
3.1. I/O x
3.1.1. HSIO 3.1.2. HVIO
3.1.1. HSIO x
3.1.1.1. I/O Supply Consideration 3.1.1.2. HSIO Bank Count
3.1.2. HVIO x
3.1.2.1. I/O Supply Consideration 3.1.2.2. HVIO Bank Count
3.4. External Memory Interface x
3.4.1. External Memory Protocol Supported in Agilex™ 5 E-Series Devices 3.4.2. External Memory Interface Support 3.4.3. External Memory Interface Migration Consideration
3.4.2. External Memory Interface Support x
3.4.2.1. DDR4 Interfaces 3.4.2.2. DDR5 Interfaces 3.4.2.3. LPDDR4 Interfaces 3.4.2.4. LPDDR5 Interfaces
3.6. Transceiver x
3.6.1. Migration Overview for Transceiver Application 3.6.2. GTS Transceiver Bank Name Change between Device Variant 3.6.3. GTS Transceiver Resources Count 3.6.4. Pre-planning the board Design for Migration Support 3.6.5. Preserving Unused PMA Lanes
3.6.3. GTS Transceiver Resources Count x
3.6.3.1. Transceiver Lane Count 3.6.3.2. GTS Transceiver Hard IP Block Count 3.6.3.3. USB3.1 Hard IP 3.6.3.4. PERST Pin and HVIO REFCLK Pin 3.6.3.5. CVP Requirement 3.6.3.6. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins 3.6.3.7. System PLL in Downbonded Quads
3.6.3.6. GTS Transmitter (TX) and GTS Receiver (RX) pin, Reference Clock Pin, and RCOMP Pins x
3.6.3.6.1. GTS TX and GTS RX pin, and Reference Clock Pin 3.6.3.6.2. RCOMP_GTS Pins
3.6.4. Pre-planning the board Design for Migration Support x
3.6.4.1. CDR Clock Output Pin for Multi and Single Transceiver Banks per Side Device 3.6.4.2. HVIO PLL as Secondary System PLL
3.7. Power x
3.7.1. Power Rails for Migration 3.7.2. Voltage Regulator Considerations for Agilex™ 5 Migration
3.8. Sensor x
3.8.1. Temperature Sensor Location Support
4. Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for Agilex™ 5 E-Series Devices
1. Introduction
2. Migration Scope
3. Functional Area
4. Quartus® Prime Software Design Migration
5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

3.1.2.1. I/O Supply Consideration

The B32A device packages are available with different HVIO bank counts. For the HVIO bank in common between the migrated devices, there is no change required to the VCCIO_HVIO supply of these HVIO banks.

Considerations taken for the VCCIO_HVIO supply to the HVIO bank locations which are different between the migrated devices:
  • If you are migrating from a device with more HVIO bank counts to a device with fewer HVIO bank counts, you can either disconnect the VCCIO_HVIO supply or maintain the VCCIO_HVIO supply connection for unavailable HVIO banks in the device with fewer HVIO bank counts.
  • If you are migrating from a device with fewer HVIO bank counts to a device with more HVIO bank counts, the VCCIO_HVIO supply of unused HVIO banks in the device with more HVIO bank counts can be connected to either GND, or any of the supported VCCIO_HVIO voltage levels of 1.8V, 2.5V, and 3.3V (default).

Refer to the Agilex™ 5 Device Pin-Out Files for more information regarding the VCCIO_HVIO pin location for Agilex™ 5 E-Series devices.

Refer to the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs for more information regarding HVIO bank feature and design guidelines for Agilex™ 5 E-Series devices.

Related Information
Level Two Title