Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

ID 813955
Date 6/06/2025
Public
Document Table of Contents

5. Document Revision History for Device Migration Guidelines: Agilex™ 5 FPGAs and SoCs E-Series

Document Version Changes
2025.06.06
  • Added the LVDS pin counts to Figure: Package Options, Migrations, and I/O Pins.
  • Updated tables:
    • DDR4
    • DDR5
    • LPDDR4
    • LPDDR5
  • Updated the Package Consideration Requirement tables in:
    • Package B15A
    • Package M16A
    • Package B18A
    • Package B23B
    • Package B23A
    • Package B32A
  • Updated Figure: Consideration Details in Package B23B.
  • Updated sections:
    • PERST Pin and HVIO REFCLK Pin
    • CDR Clock Output Pin for Multi and Single Transceiver Banks per Side Device
  • Added PERST Pin section.
2024.11.25
  • Added Pinout section.
  • Updated Figure: Consideration Details in the Package B23A.
2024.07.26
  • Added MIPI D-PHY section.
  • Updated the Package Consideration Requirement tables in:
    • Package B15A
    • Package M16A
    • Package B18A
    • Package B23B
    • Package B23A
    • Package B32A
  • Updated Table: Examples of Vertical Migration Scenarios for Each Package.
  • Updated Figure: Consideration Details in Package M16A.
  • Updated Figure: Package Options, Migrations, and I/O Pins.
  • Updated LVDS SERDES section.
2024.04.01 Initial release.