MIPI CSI-2 Intel® FPGA IP Design Example User Guide

ID 813931
Date 4/26/2024
Public

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2.4.2. Reset Scheme

Table 7.  MIPI CSI-2 Intel® FPGA IP Reset Scheme
Reset Signal Associated Clock Domain Description
rst_controller_reset_out_reset axi_clock_bridge_in_clk_clk This is MIPI CSI-2 AXI4-Streaming video input reset signal. Asserting this reset will trigger a reset to all the blocks running at axi4s_clk clock domain.
mipi_dphy_arst_reset_n mipi_dphy_ref_clk_0_clk This is MIPI D-PHY system input reset signal which is exported from MIPI D-PHY IP. For more information, refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.
mipi_dphy_reg_srst_reset_n dphy_clock_bridge_in_clk_clk This is MIPI D-PHY AXI-Lite synchronous input reset signal which is exported from MIPI D-PHY IP. For more information, refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.
mipi_dphy_LINK0_link_core_srst_reset_n mipi_dphy_LINK0_link_core_clk_clk This is MIPI D-PHY synchronous / asynchronous output reset signal for Link n which are exported from MIPI D-PHY IP. For more information, refer to the MIPI D-PHY IP User Guide: Agilex™ 5 FPGAs.
mipi_dphy_LINK0_link_core_arst_reset_n mipi_dphy_LINK0_link_core_clk_clk
mipi_dphy_LINK1_link_core_srst_reset_n mipi_dphy_LINK1_link_core_clk_clk
mipi_dphy_LINK1_link_core_arst_reset_n mipi_dphy_LINK1_link_core_clk_clk