MIPI CSI-2 Intel® FPGA IP Design Example User Guide

ID 813931
Date 4/26/2024
Public

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2.5.1. Data Signal Checking

MIPI CSI-2 is a transport protocol, and it is expected that the output of the CSI-2 RX Core should perfectly match the input of the CSI-2 TX Core. A time delay is expected between the input and the output, and this delay is variable. The other exception is that backpressure may result in different signal handshaking of tvalid and tready. However, the data beats are expected to match.

Rules which result in simulation failure:
  • Out-of-order transmission is not allowed and not possible in MIPI CSI-2.
  • This simulation does not allow for data corruption. Corruption may occur when running in hardware due to signal integrity issue and or an allowable BER due to electrical characteristics of the transmission lines.
  • The simulation does not allow for data loss. All data sent must be received or the simulation will fail.