rtl |
The folder for each synthesizable component including Platform Designer (Standard) generated IPs. |
csi2_dphy_sys.qsys |
Qsys subsystem file that contains CSI-2 RX and DPHY configuration. |
rtl/csi2_dphy_sys |
The folder that contains Platform Designer generated folder. |
csi2_dpy_sys/synth/csi2_dphy_sys.v |
Top level subsystem wrapper Verilog file. |
rtl/ip |
The folder that contains all IP files and IPs Platform Designer generated folder. |
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_rx.ip |
IP file for MIPI CSI-2 RX core. |
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_tx.ip |
IP file for MIPI CSI-2 TX core. |
ip/csi2_dphy_sys/csi2_dphy_sys_mipi_dphy.ip |
IP file for MIPI D-PHY core. |
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_reset_release_0.ip |
IP file Reset Release. |
ip/csi2_dphy_sys/csi2_dphy_sys_axi_clock_bridge.ip |
IP file Clock Bridge for AXI4S Clock. |
ip/csi2_dpy_sys/csi2_dphy_sys_dphy_clock_bridge.ip |
IP file Clock Bridge for DPHY Clock. |
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_rxsynth/csi2_dphy_sys_csi2_rx.v |
MIPI CSI-2 RX IP wrapper Verilog file. |
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_tx/synth/csi2_dphy_sys_csi2_tx.v |
MIPI CSI-2 TX IP wrapper Verilog file. |
ip/csi2_dphy_sys/csi2_dphy_sys_mipi_dphy/synth /csi2_dphy_sys_mipi_dphy.v |
MIPI D-PHY IP wrapper Verilog file. |
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_reset_release_0/synth/ csi2_dphy_sys_csi2_reset_release_0.v |
Reset Release IP wrapper Verilog file. |
ip/csi2_dphy_sys/csi2_dphy_sys_axi_clock_bridge/synth/ csi2_dphy_sys_axi_clock_bridge.v |
AXI4S Clock Bridge IP wrapper Verilog file. |
ip/csi2_dpy_sys/csi2_dphy_sys_dphy_clock_bridge/synth/ csi2_dphy_sys_dphy_clock_bridge.v |
DPHY Clock Bridge IP wrapper Verilog file. |