MIPI CSI-2 Intel® FPGA IP Design Example User Guide

ID 813931
Date 4/26/2024
Public

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2.4.3. Clocking Scheme

Table 8.  MIPI CSI-2 Intel® FPGA IP Design Example Clocking Scheme
Signal Description
axi_clock_bridge_in_clk_clk MIPI CSI-2 AXI4-Streaming video clock. This clock is used for AXI4-Streaming video processing pipeline as well as Control and Status registers.
mipi_dphy_ref_clk_0_clk MIPI D-PHY reference clock input for D-PHY PLL 0.
dphy_clock_bridge_in_clk_clk MIPI D-PHY AXI-Lite clock.
mipi_dphy_LINK0_link_core_clk_clk MIPI D-PHY RX core clock for Link n.
mipi_dphy_LINK1_link_core_clk_clk MIPI DPHY TX core clock for Link n.