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Ixiasoft
1.1.1. Design Example Parameters
Parameter | Value | Description |
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Available Design Example | ||
Select Design |
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Select the design example to be generated.
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Design Example Files | ||
Synthesis | On, Off | Turn on this option to generate the necessary files for Quartus® Prime compilation. For this release, this parameter has to be enabled to generate MIPI CSI-2 RX-only Design Example files for Quartus® Prime compilation, since simulation is not yet supported. |
Simulation | On, Off | Turn on this option to generate the necessary files for the MIPI CSI-2 RX+TX Subsystem simulation testbench. For this release, this parameter is only enabled for generating MIPI CSI-2 RX+TX Subsystem simulation testbench. MIPI CSI-2 RX-only Design Example simulation testbench is not yet supported. |
Generated HDL Format | ||
Generated File Format | Verilog, VHDL | Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files such as example testbenches and top level files for hardware demonstration are in Verilog HDL format.
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Target Development Kit | ||
Select Board | No Development Kit | Select the board for the targeted design example. No Development Kit: This option excludes all hardware aspects for the design examples. The IP core sets all pin assignments to virtual pins. |
Target Device | ||
Change Target Device | Off | Turn on this option and select the preferred device variant for the development kit.
Note: This option is only available when a Development Kit option is available in Select Board.
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