LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 7/08/2024
Public
Document Table of Contents

5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings

Table 12.  General Settings Tab
Parameter Value Description
Number of RX channels
  • RX Non-DPA—0 to 47
  • RX DPA-FIFO—0 to 47
  • RX Soft-CDR—0 to 12

Specifies the number of receiver channels in the interface.

Default is 1.

Place the refclk pin on the same I/O bank as the receiver.

Number of TX channels 0 to 47

Specifies the number of transmitter channels in the interface.

Place the refclk pin on the same I/O bank as the transmitter.

RX functional mode
  • RX Non-DPA
  • RX DPA-FIFO
  • RX Soft-CDR

Specifies the functional mode of the receiver interface.

Default is RX Non-DPA.

These options are not available if Number of RX channels is 0.

Data rate

600.0 to 1250.0

Specifies the data rate (in Mbps) of a single serial channel.

Default is 800.0.

SERDES factor
  • RX—4 or 8
  • TX—4

Select the rate of serialization and deserialization for the LVDS SERDES interface.

Default is 4.

Note: Serialization factor of 8 is available only in Agilex™ 5 FPGAs production devices.
I/O Standard
  • True Differential Signaling 1.3V
  • True Differential Signaling 1.2V
  • True Differential Signaling 1.1V
  • True Differential Signaling 1.05V
  • SLVS 1.2V
  • SLVS 1.1V

Select the I/O standard of the LVDS SERDES interface.