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1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
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4.1.4. Deserializer
The deserializer includes shift registers and parallel load registers. The deserializer sends a maximum of 8 bits to the internal logic. You can statically set the deserialization factor from ×4 to ×8 in the LVDS SERDES Intel® FPGA IP parameter editor.
The I/O element (IOE) contains two data input registers. Each data input register can operate in double data rate (DDR) or single data rate (SDR) mode. Use the GPIO Intel® FPGA IP to bypass the serializer and operate in DDR and SDR modes.
If you bypass the deserializer, you cannot use the DPA block and data realignment circuit.
Figure 11. Deserializer BypassThis figure shows the deserializer bypass path.
Mode | Description |
---|---|
SDR (×1) |
|
DDR (×2) |
|