Visible to Intel only — GUID: zca1658813170207
Ixiasoft
1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
Visible to Intel only — GUID: zca1658813170207
Ixiasoft
3.1. LVDS SERDES Transmitter Blocks
In the Agilex™ 5 LVDS SERDES transmitter, the serializer receives up to 8 bits 0 wide parallel data from the FPGA fabric.
Figure 3. LVDS SERDES Transmitter
- The serializer clocks the data into the registers and serializes the data using a multiplexer.
- The I/O PLL that drives the data to the differential buffer clocks the shift registers.
- The multiplexer transmits the MSB of the parallel data first.
Note: The PLL that drives the SERDES channel must operate in integer PLL mode.