LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 7/08/2024
Public
Document Table of Contents

7.1. LVDS SERDES IP Synthesizable Quartus® Prime Design Examples

The synthesizable design example is a compilation-ready Platform Designer system that you can include in a Quartus® Prime project.

The design example uses the parameter settings you configured in the IP parameter editor:

  • Basic LVDS SERDES IP system with transmitters or receivers
  • LVDS SERDES IP system with transmitters or receivers connected to an external PLL
Note: The synthesizable design example does not include a synthesizable driver or controller for the bitslip ports. You must create the bitslip and word aligner design portions.
Figure 33. Basic LVDS SERDES IP System with Internal PLL


If you configured the IP to use an external PLL, the generated design example connects a properly configured IOPLL Intel® FPGA IP.

Figure 34.  LVDS SERDES IP System with External PLLIn this figure, a qsys_interface_bridge provides Platform Designer connections between the IOPLL IP and the LVDS SERDES IP. For simplicity, this bridge is not shown in the other figures.


To demonstrate how to configure the PLL, the design example also provides the lvds_external_pll.qsys Platform Designer file containing a standalone version of the IOPLL IP configured to work as an external PLL. You can use lvds_external_pll.qsys, modified or unmodified, to build an LVDS SERDES design with external PLL.

Generating and Using the Design Example

To generate the synthesizable Quartus® Prime design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl -system ed_synth

The TCL script creates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Quartus® Prime software.

For more information about make_qii_design.tcl arguments, run the following command:

quartus_sh -t make_qii_design.tcl -help