Visible to Intel only — GUID: tmj1708600052651
Ixiasoft
1. Agilex™ 5 LVDS SERDES Overview
2. Agilex™ 5 LVDS SERDES Architecture
3. Agilex™ 5 LVDS SERDES Transmitter
4. Agilex™ 5 LVDS SERDES Receiver
5. Agilex™ 5 High-Speed LVDS I/O Implementation Guide
6. Agilex™ 5 LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Agilex™ 5 LVDS SERDES Design Guidelines
9. Agilex™ 5 LVDS SERDES Troubleshooting Guidelines
10. LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs Archives
11. Document Revision History for the LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs
8.1. Use PLLs in Integer PLL Mode for LVDS SERDES
8.2. Use High-Speed Clock from PLL to Clock SERDES Only
8.3. Pin Placement for Differential Channels
8.4. SERDES Pin Pairs for Soft-CDR Mode
8.5. Placing LVDS SERDES Transmitters and Receivers with External PLL
8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs
Visible to Intel only — GUID: tmj1708600052651
Ixiasoft
5.1.1. Release Information
Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Item | Description |
---|---|
IP version | 23.1.0 |
Quartus® Prime | 24.2 |
Release Date | 2024.07.08 |