LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs

ID 813929
Date 7/08/2024
Public
Document Table of Contents

5.2.2. IOPLL Parameter Values for External PLL Mode

These examples show the clocking requirements to generate output clocks for LVDS SERDES IP using the IOPLL IP. The examples set the phase shift with the assumption that the clock and data are edge-aligned at the pins of the device.
Note: For other clock and data phase relationships, Altera recommends that you first instantiate your LVDS SERDES IP interface without using the external PLL mode option. Compile the IPs in the Quartus® Prime software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the IOPLL IP parameter editor and then connect the appropriate output to the LVDS SERDES IPs.
Table 27.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate three output clocks using an IOPLL IP if you are using the non-DPA receiver.
Parameter

outclk0

(Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP)

outclk1

(Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES IP)

VCO Frequency (Connects as phout[7:0] to the ext_phout[7:0] port of LVDS SERDES IP

Frequency

data rate

data rate/16

Use the value recommended by the LVDS and IOPLL IPs

Phase shift

180°

180°/16 = 11.25

Duty cycle

50%

50%

The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.

Figure 25. Phase Relationship for External PLL Interface Signals


Table 28.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate four output clocks using an IOPLL IP if you are using the DPA or soft-CDR receiver.
Parameter

outclk0

(Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP)

outclk1

(Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES )

Not required for the soft-CDR receiver.

outclk28

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_pll_1_outclock2 port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_phout[7:0] port of LVDS SERDES IP)

Frequency

data rate

data rate/16

data rate/serialization factor

Use the value recommended by the LVDS and IOPLL IPs

Phase shift

180°

180°/16 = 11.25

180°/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

50%

50%

Table 29.   Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter and Receiver Channels (Receiver in DPA or Soft-CDR Mode) This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate three output clocks using an IOPLL IP. Use these settings if you use transmitter channels shared with receiver channels in DPA or soft-CDR mode. In this example, the transmitter and receiver interfaces are using different data rates. If the data rates are the same, you can share outclk0 and outclk1 for both the transmitter and receiver.
Parameter

outclk0

(Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP)

outclk1

(Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES IP)

Not required for the soft-CDR receiver.

VCO Frequency

(Connects as phout[7:0] to the ext_phout[7:0] ports of LVDS SERDES IP)

Frequency

data rate

data rate/16

data rate

Phase shift

180°

180°/16 = 11.25

Duty cycle

50%

50%

Table 30.  Generating Output Clocks Using an IOPLL IP for Transmitter ChannelThis table lists the parameter values you can set in the IOPLL IP parameter editor to generate three output clocks using an IOPLL IP if you use the transmitter.
Parameter

outclk0

(Connects as outclk_periph[0] to the ext_outclk_periph[0] port of LVDS SERDES IP)

outclk1

(Connects as outclk_periph[1] to the ext_outclk_periph[1] port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_phout[7:0] ports of LVDS SERDES IP)

Frequency

data rate

data rate/16

data rate

Phase shift

180°

180°/16 = 11.25

Duty cycle

50%

50%

8 Applicable when using LVDS SERDES RX in soft-CDR mode.