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1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
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5.1.4. Remote System Update Configuration Sequence
Figure 68. Remote System Update Configuration Sequence
In the following figure the blue text are states shown in the Configuration Flow Diagram.
Reconfiguration includes the following steps:
- After the device exits power-on-reset (POR), the boot ROM loads flash memory from the first valid decision firmware from one of the copies at addresses 0, 512 K, 1024 K, or 1536 K to initialize the SDM. This firmware is part of the initial RSU flash image. ( Refer to Step 2 of Guidelines for Performing Remote System Update Functions for Non-HPS for step-by-step details for programming the initial RSU flash image into the flash.)
If you trigger the reconfiguration with a pulse of nCONFIG low, the SDM loads the decision firmware.
- The optional Direct to Factory Image pin controls whether the SDM firmware loads the factory or application image. You can assign the Direct to Factory Image input to any unused SDM pin. The SDM loads the application image if you do not assign this pin.
- The configuration pointer block in the flash device maintains a list of pointers to the application images.
- When loading an application image, the SDM traverses the pointer block in reverse order. The SDM loads the highest priority image. When image loading completes, the device enters user mode.
- If loading the newest (highest priority) image is unsuccessful, the SDM tries the next application image from the list. If none of the application images load successfully, the SDM loads the factory image.
Note: If loading the factory image fails, you can recover by reprogramming the quad SPI flash with the initial RSU flash image using the JTAG interface.Note: For every unsuccessful configuration, the nSTATUS asserts a low pulse to indicate configuration failure and the SDM proceeds to load the next image automatically, do not assert nCONFIG low to attempt to load the next application image.
- During the remote update to other application image or factory image, the SDM loads the decision firmware.
Note:
You must keep nCONFIG high until the device enters the user mode.
- Keep the nCONFIG signal high after the device powers up and throughout the entire device configuration to load an application or factory image.
- Keep the nCONFIG signal high during the remote update to other application image or factory image by using the RSU_IMAGE_UPDATE command.
You drive nCONFIG low only when the device is in user mode to trigger the reconfiguration.