Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

ID 813773
Date 4/01/2024
Public

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3.1.7.1.1. Generating and Programming a .pof into CFI Flash

The Quartus® Prime software generates the .sof when you compile your design. You use the .sof to generate the .pof. This process includes the following steps:

  1. Generating a .pof for the Parallel Flash Loader II Intel® FPGA IP using the Quartus® Prime File > Programming File Generator.
  2. Using the Quartus® Prime Programmer to write the Agilex™ 5 device .pof to the flash device.
Figure 24. Programming the CFI Flash Memory with the JTAG Interface

The Parallel Flash Loader II Intel® FPGA IP supports dual flash memory devices in burst read mode to achieve faster configuration times. You can connect two MT28EW CFI flash memory devices to the host in parallel using the same data bus, clock, and control signals. Intel does not support connecting two of non-MT28W CFI flash memory devices to the Parallel Flash Loader II Intel® FPGA IP in parallel. During FPGA configuration, the AVST_CLK frequency is four times faster than the flash_clk frequency.

Figure 25.  Parallel Flash Loader II Intel® FPGA IP with Dual MT28EW CFI Flash Memory DevicesThe flash memory devices must have the same memory density from the same device family and manufacturer.