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1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
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3.1.7.5.1. Converting .sof to .pof File
You can use the Programming File Generator to convert the .sof file to a .pof. The Programming File Generator options change dynamically according to your device and configuration mode selection.
Complete these steps to convert .sof file to a .pof:
- Click File > Programming File Generator.
- For Device family select Agilex™ 5.
- For Configuration mode select Avalon® -ST configuration scheme that you plan to use.
- For Output directory, click Browse to select your output file directory.
- For Name specify a name for your output file.
- On the Output Files tab, enable the checkbox for generation of the file or files you want to generate.
Figure 35. Programming File Generator Output Files Tab
- To specify a .sof that contains the configuration bitstream, on the Input Files tab, click Add Bitstream.
Figure 36. Input Files Tab
- To include raw data, click Add Raw Data and specify a Hexadecimal ( Intel® -Format) Output File (.hex) or binary (.bin) file. This step is optional.
- On the Configuration Device tab, click Add device. The Add Device dialog box appears. Select your flash device from the drop-down list of available parallel flash devices.
- Click OPTIONS and then Edit. In the Edit Partition dialog box specify the Start address of the Options in flash memory. This address must match the address you specify for What is the byte address of the option bits, in hex? when specifying the Parallel Flash Loader II Intel® FPGA IP parameters. Ensure that the option bits sector does not overlap with the configuration data pages and that the start address is on an 8 KB boundary.
Figure 37. Edit Partition: OPTIONS for Flash Device
- With the flash device selected, click Add Partition to specify a partition in flash memory.
Figure 38. Add Flash Device and Partition
- For Name select a Partition name.
- For Input File specify the .sof.
- From the Page dropdown list, select the page to write this .sof.
- For Address mode select the addressing mode to use.
The following modes are available:
- Auto— For the tool to automatically allocates a block in the flash device to store the data.
- Block—To specify the start and end address of the flash partition.
- Start—To specify the start address of the partition. The tool assigns the end address of the partition based on the input data size.
- For Block and Start options, specify the address information.